Expose debugBreakCycle through swig and get rid of

the Debug param context

--HG--
extra : convert_revision : 40e9dcfa9faedbe0c90a43f908f20a7c14ded6a4

7 files changed, 35 insertions, 36 deletions

diff --git a/src/SConscript b/src/SConscript
index 385047f7f..9d54174ab 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -129,6 +129,7 @@ base_sources = Split('''
 
         mem/cache/cache_builder.cc
 
+        python/swig/debug_wrap.cc
         python/swig/main_wrap.cc
 
 	sim/builder.cc
diff --git a/src/python/SConscript b/src/python/SConscript
index 5c351c32a..be6248bab 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -98,11 +98,17 @@ pyzip_files.append('m5/defines.py')
 pyzip_files.append('m5/info.py')
 pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py'))
 
+env.Command(['swig/debug_wrap.cc', 'm5/internal/debug.py'],
+            'swig/debug.i',
+            '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
+            '-o ${TARGETS[0]} $SOURCES')
+
 env.Command(['swig/main_wrap.cc', 'm5/internal/main.py'],
             'swig/main.i',
             '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
             '-o ${TARGETS[0]} $SOURCES')
 
+pyzip_dep_files.append('m5/internal/debug.py')
 pyzip_dep_files.append('m5/internal/main.py')
 
 # Action function to build the zip archive.  Uses the PyZipFile module
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 1e224c0cf..114c668a6 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -275,7 +275,8 @@ def main():
     objects.Statistics.text_file = options.stats_file
 
     # set debugging options
-    objects.Debug.break_cycles = options.debug_break
+    for when in options.debug_break:
+        internal.debug.schedBreakCycle(int(when))
 
     # set tracing options
     objects.Trace.flags = options.trace_flags
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 8e8d87f6d..b6123f192 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -5,7 +5,6 @@ from Serialize import Statreset
 from Statistics import Statistics
 from Trace import Trace
 from ExeTrace import ExecutionTrace
-from Debug import Debug
 
 class Root(SimObject):
     type = 'Root'
@@ -22,4 +21,3 @@ class Root(SimObject):
     trace = Trace()
     exetrace = ExecutionTrace()
     serialize = Serialize()
-    debug = Debug()
diff --git a/src/python/swig/debug.i b/src/python/swig/debug.i
new file mode 100644
index 000000000..8da2974ca
--- /dev/null
+++ b/src/python/swig/debug.i
@@ -0,0 +1,19 @@
+%module debug
+
+%{
+// include these files when compiling debug_wrap.cc
+#include "sim/host.hh"
+%}
+
+%include "stdint.i"
+%include "sim/host.hh"
+
+%inline %{
+extern void schedBreakCycle(Tick when);
+%}
+
+%wrapper %{
+// fix up module name to reflect the fact that it's inside the m5 package
+#undef SWIG_name
+#define SWIG_name "m5.internal._debug"
+%}
diff --git a/src/sim/debug.cc b/src/sim/debug.cc
index be9566836..84ab1074d 100644
--- a/src/sim/debug.cc
+++ b/src/sim/debug.cc
@@ -94,45 +94,17 @@ DebugBreakEvent::description()
 }
 
 //
-// Parameter context for global debug options
-//
-class DebugContext : public ParamContext
-{
-  public:
-    DebugContext(const string &_iniSection)
-        : ParamContext(_iniSection) {}
-    void checkParams();
-};
-
-DebugContext debugParams("debug");
-
-VectorParam<Tick> break_cycles(&debugParams, "break_cycles",
-                                 "cycle(s) to create breakpoint events");
-
-void
-DebugContext::checkParams()
-{
-    if (break_cycles.isValid()) {
-        vector<Tick> &cycles = break_cycles;
-
-        vector<Tick>::iterator i = cycles.begin();
-        vector<Tick>::iterator end = cycles.end();
-
-        for (; i < end; ++i)
-            new DebugBreakEvent(&mainEventQueue, *i);
-    }
-}
-
-//
 // handy function to schedule DebugBreakEvent on main event queue
 // (callable from debugger)
 //
-void sched_break_cycle(Tick when)
+void
+schedBreakCycle(Tick when)
 {
     new DebugBreakEvent(&mainEventQueue, when);
 }
 
-void eventq_dump()
+void
+eventqDump()
 {
     mainEventQueue.dump();
 }
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 6037283a4..17209ac20 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -119,6 +119,7 @@ abortHandler(int sigtype)
 
 extern "C" {
 void init_main();
+void init_debug();
 }
 
 int
@@ -157,8 +158,9 @@ main(int argc, char **argv)
     Py_Initialize();
     PySys_SetArgv(argc, argv);
 
-    // initialize SWIG 'm5.internal.main' module
+    // initialize SWIG modules
     init_main();
+    init_debug();
 
     PyRun_SimpleString("import m5.main");
     PyRun_SimpleString("m5.main.main()");