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authorGabe Black <gblack@eecs.umich.edu>2009-04-19 03:22:38 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-04-19 03:22:38 -0700
commitbdd55ec8b6eda4b46288d8f85a5a9fa603cd6ab4 (patch)
tree7e3e589fb17df300bde7eea42cca14e614f8ea91 /src
parentd86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152 (diff)
downloadgem5-bdd55ec8b6eda4b46288d8f85a5a9fa603cd6ab4.tar.xz
X86: Implement the save machine status word instruction (SMSW).
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa4
-rw-r--r--src/arch/x86/isa/insts/system/control_registers.py15
2 files changed, 17 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index e55756fec..c344ee550 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -125,7 +125,7 @@
0x6: skinit();
0x7: invlpga();
}
- 0x4: smsw_Rv();
+ 0x4: Inst::SMSW(Rv);
0x6: Inst::LMSW(Rv);
0x7: decode MODRM_RM {
0x0: Inst::SWAPGS();
@@ -155,7 +155,7 @@
default: Inst::LIDT(M);
}
}
- 0x4: smsw_Mw();
+ 0x4: Inst::SMSW(Mw);
0x6: Inst::LMSW(Mw);
0x7: Inst::INVLPG(M);
default: Inst::UD2();
diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py
index c09cdf6e8..82811bb07 100644
--- a/src/arch/x86/isa/insts/system/control_registers.py
+++ b/src/arch/x86/isa/insts/system/control_registers.py
@@ -68,4 +68,19 @@ def macroop LMSW_P {
or t1, t1, t2, dataSize=8
wrcr 0, t1, dataSize=8
};
+
+def macroop SMSW_R {
+ rdcr reg, 0
+};
+
+def macroop SMSW_M {
+ rdcr t1, 0
+ st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop SMSW_P {
+ rdcr t1, 0
+ rdip t7, dataSize=asz
+ st t1, seg, riprel, disp, dataSize=2
+};
'''