make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered

across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.

29 files changed, 84 insertions, 110 deletions

diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index f629d982a..6f4f5a748 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -87,7 +87,7 @@ handleLockedWrite(XC *xc, Request *req)
             if (stCondFailures % 100000 == 0) {
                 warn("cpu %d: %d consecutive "
                      "store conditional failures\n",
-                     xc->readCpuId(), stCondFailures);
+                     xc->cpuId(), stCondFailures);
             }
 
             // store conditional failed already, so don't issue it to mem
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 07dc9d588..5877b1439 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -85,7 +85,7 @@ handleLockedWrite(XC *xc, Request *req)
             if (stCondFailures % 10 == 0) {
                 warn("%i: cpu %d: %d consecutive "
                      "store conditional failures\n",
-                     curTick, xc->readCpuId(), stCondFailures);
+                     curTick, xc->cpuId(), stCondFailures);
             }
 
             if (stCondFailures == 5000) {
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index e1276b812..6961a24e9 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -257,11 +257,11 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
         temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
         // Check that the CPU array is fully populated
         // (by calling getNumCPus())
-        assert(sys->getNumCPUs() > tc->readCpuId());
+        assert(sys->getNumCPUs() > tc->cpuId());
 
-        temp |= tc->readCpuId()  << STS::shft_id;
+        temp |= tc->cpuId()  << STS::shft_id;
 
-        for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
+        for (x = tc->cpuId() & ~3; x < sys->threadContexts.size(); x++) {
             switch (sys->threadContexts[x]->status()) {
               case ThreadContext::Active:
                 temp |= STS::st_run << (STS::shft_fsm0 -
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 5db678919..17374fa0c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -654,7 +654,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
         */
         // Force the access to be uncacheable.
         req->setFlags(req->getFlags() | UNCACHEABLE);
-        req->setPaddr(x86LocalAPICAddress(tc->readCpuId(), paddr - baseAddr));
+        req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
     }
 #endif
     return NoFault;
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index ef9b54f3f..f98c6af8e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -63,7 +63,7 @@ class BaseCPU(MemObject):
     abstract = True
 
     system = Param.System(Parent.any, "system object")
-    cpu_id = Param.Int("CPU identifier")
+    cpu_id = Param.Int(-1, "CPU identifier")
     numThreads = Param.Unsigned(1, "number of HW thread contexts")
 
     function_trace = Param.Bool(False, "Enable function trace")
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 8c461cccb..3e899d993 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -94,21 +94,29 @@ CPUProgressEvent::description() const
 
 #if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
-    : MemObject(p), clock(p->clock), instCnt(0), interrupts(p->interrupts),
+    : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+      interrupts(p->interrupts),
       number_of_threads(p->numThreads), system(p->system),
       phase(p->phase)
 #else
 BaseCPU::BaseCPU(Params *p)
-    : MemObject(p), clock(p->clock),
+    : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
       number_of_threads(p->numThreads), system(p->system),
       phase(p->phase)
 #endif
 {
 //    currentTick = curTick;
 
+    // if Python did not provide a valid ID, do it here
+    if (_cpuId == -1 ) {
+        _cpuId = cpuList.size();
+    }
+
     // add self to global list of CPUs
     cpuList.push_back(this);
 
+    DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
+
     if (number_of_threads > maxThreadsPerCPU)
         maxThreadsPerCPU = number_of_threads;
 
@@ -278,13 +286,9 @@ BaseCPU::registerThreadContexts()
         ThreadContext *tc = threadContexts[i];
 
 #if FULL_SYSTEM
-        int id = params()->cpu_id;
-        if (id != -1)
-            id += i;
-
-        tc->setCpuId(system->registerThreadContext(tc, id));
+        system->registerThreadContext(tc);
 #else
-        tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
+        tc->getProcessPtr()->registerThreadContext(tc);
 #endif
     }
 }
@@ -315,6 +319,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
 {
     assert(threadContexts.size() == oldCPU->threadContexts.size());
 
+    _cpuId = oldCPU->cpuId();
+
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *newTC = threadContexts[i];
         ThreadContext *oldTC = oldCPU->threadContexts[i];
@@ -323,12 +329,12 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
 
         CpuEvent::replaceThreadContext(oldTC, newTC);
 
-        assert(newTC->readCpuId() == oldTC->readCpuId());
+        assert(newTC->cpuId() == oldTC->cpuId());
 #if FULL_SYSTEM
-        system->replaceThreadContext(newTC, newTC->readCpuId());
+        system->replaceThreadContext(newTC, newTC->cpuId());
 #else
         assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
-        newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
+        newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->cpuId());
 #endif
 
         if (DTRACE(Context))
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 2d25c9e56..f39759605 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -80,8 +80,16 @@ class BaseCPU : public MemObject
     Tick clock;
     // @todo remove me after debugging with legion done
     Tick instCnt;
+    // every cpu has an id, put it in the base cpu
+    // Set at initialization, only time a cpuId might change is during a
+    // takeover (which should be done from within the BaseCPU anyway, 
+    // therefore no setCpuId() method is provided
+    int _cpuId;
 
   public:
+    /** Reads this CPU's ID. */
+    int cpuId() { return _cpuId; }
+
 //    Tick currentTick;
     inline Tick frequency() const { return Clock::Frequency / clock; }
     inline Tick ticks(int numCycles) const { return clock * numCycles; }
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b03a2f63e..e0de3a372 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -412,7 +412,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
     void dump(std::string &outstring);
 
     /** Read this CPU's ID. */
-    int readCpuId() { return cpu->readCpuId(); }
+    int cpuId() { return cpu->cpuId(); }
 
     /** Returns the fault type. */
     Fault getFault() { return fault; }
@@ -868,7 +868,7 @@ BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->readCpuId(), threadNumber);
+    req->setThreadContext(thread->cpuId(), threadNumber);
 
     fault = cpu->translateDataReadReq(req, thread);
 
@@ -887,7 +887,7 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
-    req->setThreadContext(thread->readCpuId(), threadNumber);
+    req->setThreadContext(thread->cpuId(), threadNumber);
 
     fault = cpu->translateDataReadReq(req, thread);
 
@@ -942,7 +942,7 @@ BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, vaddr, size, flags, PC);
-    req->setThreadContext(thread->readCpuId(), threadNumber);
+    req->setThreadContext(thread->cpuId(), threadNumber);
 
     fault = cpu->translateDataWriteReq(req, thread);
 
@@ -966,7 +966,7 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     reqMade = true;
     Request *req = new Request();
     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
-    req->setThreadContext(thread->readCpuId(), threadNumber);
+    req->setThreadContext(thread->cpuId(), threadNumber);
 
     fault = cpu->translateDataWriteReq(req, thread);
 
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 33c70569a..9f6fa2b6d 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -152,7 +152,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
         memReq = new Request(inst->threadNumber, fetch_PC,
                              sizeof(uint32_t),
                              IFETCH_FLAGS(thread->readPC()),
-                             fetch_PC, thread->readCpuId(), inst->threadNumber);
+                             fetch_PC, thread->cpuId(), inst->threadNumber);
 
         bool succeeded = translateInstReq(memReq);
 
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 75ac959db..a74de20b9 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -82,7 +82,7 @@ class CheckerThreadContext : public ThreadContext
         checkerTC->setCpuId(id);
     }
 
-    int readCpuId() { return actualTC->readCpuId(); }
+    int cpuId() { return actualTC->cpuId(); }
 
     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 1b7a3a17c..b7cf4f1c0 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -62,7 +62,7 @@ class BaseCPUParams;
 using namespace TheISA;
 
 BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
-    : BaseCPU(params), cpuId(0)
+    : BaseCPU(params)
 {
 }
 
@@ -404,7 +404,6 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
 #endif
         // Give the thread the TC.
         this->thread[i]->tc = tc;
-        this->thread[i]->setCpuId(params->cpu_id);
 
         // Add the TC to the CPU's list of TC's.
         this->threadContexts.push_back(tc);
@@ -611,7 +610,7 @@ FullO3CPU<Impl>::init()
         }
 
 #if FULL_SYSTEM
-        TheISA::initCPU(src_tc, src_tc->readCpuId());
+        TheISA::initCPU(src_tc, src_tc->cpuId());
 #endif
     }
 
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d1cc8bea5..c60c20d55 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -74,15 +74,6 @@ class BaseO3CPU : public BaseCPU
     BaseO3CPU(BaseCPUParams *params);
 
     void regStats();
-
-    /** Sets this CPU's ID. */
-    void setCpuId(int id) { cpuId = id; }
-
-    /** Reads this CPU's ID. */
-    int readCpuId() { return cpuId; }
-
-  protected:
-    int cpuId;
 };
 
 /**
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 0b5ce9380..35031663e 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -593,7 +593,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
     // Set the appropriate read size and flags as well.
     // Build request here.
     RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
-                                     fetch_PC, cpu->readCpuId(), tid);
+                                     fetch_PC, cpu->cpuId(), tid);
 
     memReq[tid] = mem_req;
 
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index c529b002b..d571d25db 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -75,11 +75,8 @@ class O3ThreadContext : public ThreadContext
     /** Returns a pointer to this CPU. */
     virtual BaseCPU *getCpuPtr() { return cpu; }
 
-    /** Sets this CPU's ID. */
-    virtual void setCpuId(int id) { cpu->setCpuId(id); }
-
     /** Reads this CPU's ID. */
-    virtual int readCpuId() { return cpu->readCpuId(); }
+    virtual int cpuId() { return cpu->cpuId(); }
 
 #if FULL_SYSTEM
     /** Returns a pointer to the system. */
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index d8ec70bb8..853ee2c63 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -63,7 +63,6 @@ O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
     // copy over functional state
     setStatus(old_context->status());
     copyArchRegs(old_context);
-    setCpuId(old_context->readCpuId());
 
 #if !FULL_SYSTEM
     thread->funcExeInst = old_context->readFuncExeInst();
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index 8c634f67e..1f0e7a3bb 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -77,7 +77,7 @@ struct O3ThreadState : public ThreadState {
 
 #if FULL_SYSTEM
     O3ThreadState(O3CPU *_cpu, int _thread_num)
-        : ThreadState(_cpu, -1, _thread_num),
+        : ThreadState(_cpu, _thread_num),
           cpu(_cpu), inSyscall(0), trapPending(0)
     {
         if (cpu->params()->profile) {
@@ -96,7 +96,7 @@ struct O3ThreadState : public ThreadState {
     }
 #else
     O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid)
-        : ThreadState(_cpu, -1, _thread_num, _process, _asid),
+        : ThreadState(_cpu, _thread_num, _process, _asid),
           cpu(_cpu), inSyscall(0), trapPending(0)
     { }
 #endif
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 491e6ba93..8fce61d4f 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -116,10 +116,6 @@ class OzoneCPU : public BaseCPU
 
         BaseCPU *getCpuPtr();
 
-        void setCpuId(int id);
-
-        int readCpuId() { return thread->readCpuId(); }
-
         TheISA::ITB *getITBPtr() { return cpu->itb; }
 
         TheISA::DTB * getDTBPtr() { return cpu->dtb; }
@@ -353,12 +349,6 @@ class OzoneCPU : public BaseCPU
   public:
     BaseCPU *getCpuPtr() { return this; }
 
-    void setCpuId(int id) { cpuId = id; }
-
-    int readCpuId() { return cpuId; }
-
-    int cpuId;
-
     void switchOut();
     void signalSwitched();
     void takeOverFrom(BaseCPU *oldCPU);
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index a7efa3596..52376afd8 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -417,7 +417,7 @@ OzoneCPU<Impl>::init()
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, tc->readCpuId());
+        TheISA::initCPU(tc, tc->cpuId());
     }
 #endif
     frontEnd->renameTable.copyFrom(thread.renameTable);
@@ -803,7 +803,7 @@ OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
     // copy over functional state
     setStatus(old_context->status());
     copyArchRegs(old_context);
-    setCpuId(old_context->readCpuId());
+    setCpuId(old_context->cpuId());
 
     thread->setInst(old_context->getInst());
 #if !FULL_SYSTEM
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 198ce0308..df3609e27 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -477,7 +477,7 @@ FrontEnd<Impl>::fetchCacheLine()
     // Setup the memReq to do a read of the first isntruction's address.
     // Set the appropriate read size and flags as well.
     memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
-                         PC, cpu->readCpuId(), 0);
+                         PC, cpu->cpuId(), 0);
 
     // Translate the instruction request.
     fault = cpu->translateInstReq(memReq, thread);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 30f4a5c5e..5e8ab9443 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -79,13 +79,12 @@ void
 AtomicSimpleCPU::init()
 {
     BaseCPU::init();
-    cpuId = tc->readCpuId();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, cpuId);
+        TheISA::initCPU(tc, _cpuId);
     }
 #endif
     if (hasPhysMemPort) {
@@ -94,9 +93,9 @@ AtomicSimpleCPU::init()
         physmemPort.getPeerAddressRanges(pmAddrList, snoop);
         physMemAddr = *pmAddrList.begin();
     }
-    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
-    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
-    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
+    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
+    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
+    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
 }
 
 bool
@@ -237,10 +236,9 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    cpuId = tc->readCpuId();
-    ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT
-    data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too
-    data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too
+    ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
+    data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
+    data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
 }
 
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index dc736c22e..6e72b8f6c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -121,7 +121,6 @@ class BaseSimpleCPU : public BaseCPU
      */
     ThreadContext *tc;
   protected:
-    int cpuId;
 
     enum Status {
         Idle,
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index a6059f55f..247899ca8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -57,13 +57,12 @@ void
 TimingSimpleCPU::init()
 {
     BaseCPU::init();
-    cpuId = tc->readCpuId();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
         ThreadContext *tc = threadContexts[i];
 
         // initialize CPU, including PC
-        TheISA::initCPU(tc, cpuId);
+        TheISA::initCPU(tc, _cpuId);
     }
 #endif
 }
@@ -203,7 +202,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    cpuId = tc->readCpuId();
+    _cpuId = tc->cpuId();
     previousTick = curTick;
 }
 
@@ -250,7 +249,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    cpuId, /* thread ID */ 0);
+                    _cpuId, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -301,7 +300,7 @@ TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
         int size, unsigned flags)
 {
     Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
 
     if (traceData) {
         traceData->setAddr(vaddr);
@@ -373,7 +372,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 {
     Request *req =
         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
-                    cpuId, /* thread ID */ 0);
+                    _cpuId, /* thread ID */ 0);
 
     if (traceData) {
         traceData->setAddr(req->getVaddr());
@@ -442,7 +441,7 @@ TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
         int size, unsigned flags)
 {
     Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
+        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
 
     if (traceData) {
         traceData->setAddr(vaddr);
@@ -528,7 +527,7 @@ TimingSimpleCPU::fetch()
 
     if (!fromRom) {
         Request *ifetch_req = new Request();
-        ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
+        ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
         Fault fault = setupFetchRequest(ifetch_req);
 
         ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 68683e568..6034ca120 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -63,7 +63,7 @@ using namespace std;
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::ITB *_itb, TheISA::DTB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
+    : ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
       dtb(_dtb)
 
 {
@@ -93,7 +93,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 #else
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
                            TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
-    : ThreadState(_cpu, -1, _thread_num, _process, _asid),
+    : ThreadState(_cpu, _thread_num, _process, _asid),
       cpu(_cpu), itb(_itb), dtb(_dtb)
 {
     regs.clear();
@@ -104,9 +104,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
 
 SimpleThread::SimpleThread()
 #if FULL_SYSTEM
-    : ThreadState(NULL, -1, -1)
+    : ThreadState(NULL, -1)
 #else
-    : ThreadState(NULL, -1, -1, NULL, -1)
+    : ThreadState(NULL, -1, NULL, -1)
 #endif
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
@@ -178,7 +178,6 @@ SimpleThread::copyState(ThreadContext *oldContext)
     // copy over functional state
     _status = oldContext->status();
     copyArchRegs(oldContext);
-    cpuId = oldContext->readCpuId();
 #if !FULL_SYSTEM
     funcExeInst = oldContext->readFuncExeInst();
 #endif
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 10c94027d..58912c564 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -74,8 +74,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
     if (npc1 != npc2)
         panic("NPCs doesn't match, one: %#x, two: %#x", npc1, npc2);
 
-    int id1 = one->readCpuId();
-    int id2 = two->readCpuId();
+    int id1 = one->cpuId();
+    int id2 = two->cpuId();
     if (id1 != id2)
         panic("CPU ids don't match, one: %d, two: %d", id1, id2);
 }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 2b9f41b70..d06194012 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -115,9 +115,7 @@ class ThreadContext
 
     virtual BaseCPU *getCpuPtr() = 0;
 
-    virtual void setCpuId(int id) = 0;
-
-    virtual int readCpuId() = 0;
+    virtual int cpuId() = 0;
 
     virtual TheISA::ITB *getITBPtr() = 0;
 
@@ -300,9 +298,7 @@ class ProxyThreadContext : public ThreadContext
 
     BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
 
-    void setCpuId(int id) { actualTC->setCpuId(id); }
-
-    int readCpuId() { return actualTC->readCpuId(); }
+    int cpuId() { return actualTC->cpuId(); }
 
     TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
 
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 8d519c563..47841922e 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -43,15 +43,15 @@
 #endif
 
 #if FULL_SYSTEM
-ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid)
-    : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
+ThreadState::ThreadState(BaseCPU *cpu, int _tid)
+    : baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
       profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
       kernelStats(NULL), physPort(NULL), virtPort(NULL),
       microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
 #else
-ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
+ThreadState::ThreadState(BaseCPU *cpu, int _tid, Process *_process,
                          short _asid)
-    : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
+    : baseCpu(cpu), tid(_tid), lastActivate(0), lastSuspend(0),
       port(NULL), process(_process), asid(_asid),
       microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
 #endif
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 1b667f72a..f3f154de3 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -34,6 +34,7 @@
 #include "arch/types.hh"
 #include "cpu/profile.hh"
 #include "cpu/thread_context.hh"
+#include "cpu/base.hh"
 
 #if !FULL_SYSTEM
 #include "mem/mem_object.hh"
@@ -51,7 +52,6 @@ namespace TheISA {
 };
 #endif
 
-class BaseCPU;
 class Checkpoint;
 class Port;
 class TranslatingPort;
@@ -66,9 +66,9 @@ struct ThreadState {
     typedef ThreadContext::Status Status;
 
 #if FULL_SYSTEM
-    ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
+    ThreadState(BaseCPU *cpu, int _tid);
 #else
-    ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
+    ThreadState(BaseCPU *cpu, int _tid, Process *_process,
                 short _asid);
 #endif
 
@@ -78,9 +78,7 @@ struct ThreadState {
 
     void unserialize(Checkpoint *cp, const std::string &section);
 
-    void setCpuId(int id) { cpuId = id; }
-
-    int readCpuId() { return cpuId; }
+    int cpuId() { return baseCpu->cpuId(); }
 
     void setTid(int id) { tid = id; }
 
@@ -171,10 +169,6 @@ struct ThreadState {
     // Pointer to the base CPU.
     BaseCPU *baseCpu;
 
-    // ID of this context w.r.t. the System or Process object to which
-    // it belongs.  For full-system mode, this is the system CPU ID.
-    int cpuId;
-
     // Index of hardware thread context on the CPU that this represents.
     int tid;
 
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7b830d0f7..41075e9d0 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -166,13 +166,12 @@ bool System::breakpoint()
 }
 
 int
-System::registerThreadContext(ThreadContext *tc, int id)
+System::registerThreadContext(ThreadContext *tc)
 {
-    if (id == -1) {
-        for (id = 0; id < threadContexts.size(); id++) {
-            if (!threadContexts[id])
-                break;
-        }
+    int id;
+    for (id = 0; id < threadContexts.size(); id++) {
+        if (!threadContexts[id])
+            break;
     }
 
     if (threadContexts.size() <= id)
diff --git a/src/sim/system.hh b/src/sim/system.hh
index cdd5bebb0..f67d39c67 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -219,7 +219,7 @@ class System : public SimObject
 
 #endif // FULL_SYSTEM
 
-    int registerThreadContext(ThreadContext *tc, int tcIndex);
+    int registerThreadContext(ThreadContext *tc);
     void replaceThreadContext(ThreadContext *tc, int tcIndex);
 
     void serialize(std::ostream &os);