X86: Make the I8259 decipher the commands it's given, and add some of it's registers.

2 files changed, 154 insertions, 2 deletions

diff --git a/src/dev/x86/i8259.cc b/src/dev/x86/i8259.cc
index 62698c0eb..ed9b429c8 100644
--- a/src/dev/x86/i8259.cc
+++ b/src/dev/x86/i8259.cc
@@ -28,19 +28,156 @@
  * Authors: Gabe Black
  */
 
+#include "base/bitfield.hh"
 #include "dev/x86/i8259.hh"
 
 Tick
 X86ISA::I8259::read(PacketPtr pkt)
 {
-    DPRINTF(I8259, "Reading from PIC device.\n");
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - pioAddr)
+    {
+      case 0x0:
+        if (readIRR) {
+            DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
+            pkt->set(IRR);
+        } else {
+            DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
+            pkt->set(ISR);
+        }
+        break;
+      case 0x1:
+        DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
+        pkt->set(IMR);
+        break;
+    }
     return latency;
 }
 
 Tick
 X86ISA::I8259::write(PacketPtr pkt)
 {
-    DPRINTF(I8259, "Writing to PIC device.\n");
+    assert(pkt->getSize() == 1);
+    uint8_t val = pkt->get<uint8_t>();
+    switch (pkt->getAddr() - pioAddr) {
+      case 0x0:
+        if (bits(val, 4)) {
+            DPRINTF(I8259, "Received initialization command word 1.\n");
+            IMR = 0;
+            edgeTriggered = bits(val, 3);
+            DPRINTF(I8259, "%s triggered mode.\n",
+                    edgeTriggered ? "Edge" : "Level");
+            cascadeMode = !bits(val, 1);
+            DPRINTF(I8259, "%s mode.\n",
+                    cascadeMode ? "Cascade" : "Single");
+            expectICW4 = bits(val, 0);
+            initControlWord = 1;
+            DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
+        } else if (bits(val, 4, 3) == 0) {
+            DPRINTF(I8259, "Received operation command word 2.\n");
+            switch (bits(val, 7, 5)) {
+              case 0x0:
+                DPRINTF(I8259,
+                        "Subcommand: Rotate in auto-EOI mode (clear).\n");
+                break;
+              case 0x1:
+                DPRINTF(I8259, "Subcommand: Nonspecific EOI.\n");
+                break;
+              case 0x2:
+                DPRINTF(I8259, "Subcommand: No operation.\n");
+                break;
+              case 0x3:
+                DPRINTF(I8259, "Subcommand: Specific EIO.");
+                DPRINTF(I8259, "Reset In-Service bit %d.\n", bits(val, 2, 0));
+                break;
+              case 0x4:
+                DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
+                break;
+              case 0x5:
+                DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
+                break;
+              case 0x6:
+                DPRINTF(I8259, "Subcommand: Set priority command.\n");
+                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
+                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
+                break;
+              case 0x7:
+                DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
+                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
+                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
+                break;
+            }
+        } else if (bits(val, 4, 3) == 1) {
+            DPRINTF(I8259, "Received operation command word 3.\n");
+            if (bits(val, 7)) {
+                DPRINTF(I8259, "%s special mask mode.\n",
+                        bits(val, 6) ? "Set" : "Clear");
+            }
+            if (bits(val, 1)) {
+                readIRR = bits(val, 0);
+                DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
+            }
+        }
+        break;
+      case 0x1:
+        switch (initControlWord) {
+          case 0x0:
+            DPRINTF(I8259, "Received operation command word 1.\n");
+            DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
+            IMR = val;
+            break;
+          case 0x1:
+            DPRINTF(I8259, "Received initialization command word 2.\n");
+            DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
+                    val & ~mask(3), val | mask(3));
+            if (cascadeMode) {
+                initControlWord++;
+            } else {
+                initControlWord = 0;
+            }
+            break;
+          case 0x2:
+            DPRINTF(I8259, "Received initialization command word 3.\n");
+            if (master) {
+                DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
+                        bits(val, 0) ? " 0" : "",
+                        bits(val, 1) ? " 1" : "",
+                        bits(val, 2) ? " 2" : "",
+                        bits(val, 3) ? " 3" : "",
+                        bits(val, 4) ? " 4" : "",
+                        bits(val, 5) ? " 5" : "",
+                        bits(val, 6) ? " 6" : "",
+                        bits(val, 7) ? " 7" : "");
+            } else {
+                DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
+            }
+            if (expectICW4)
+                initControlWord++;
+            else
+                initControlWord = 0;
+            break;
+          case 0x3:
+            DPRINTF(I8259, "Received initialization command word 4.\n");
+            if (bits(val, 4)) {
+                DPRINTF(I8259, "Special fully nested mode.\n");
+            } else {
+                DPRINTF(I8259, "Not special fully nested mode.\n");
+            }
+            if (bits(val, 3) == 0) {
+                DPRINTF(I8259, "Nonbuffered.\n");
+            } else if (bits(val, 2) == 0) {
+                DPRINTF(I8259, "Buffered.\n");
+            } else {
+                DPRINTF(I8259, "Unrecognized buffer mode.\n");
+            }
+            DPRINTF(I8259, "%s End Of Interrupt.\n",
+                    bits(val, 1) ? "Automatic" : "Normal");
+            DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
+            initControlWord = 0;
+            break;
+        }
+        break;
+    }
     return latency;
 }
 
diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh
index a2f245513..131adc93f 100644
--- a/src/dev/x86/i8259.hh
+++ b/src/dev/x86/i8259.hh
@@ -43,6 +43,19 @@ class I8259 : public BasicPioDevice
     Tick latency;
     bool master;
 
+    // Interrupt Request Register
+    uint8_t IRR;
+    // In Service Register
+    uint8_t ISR;
+    // Interrupt Mask Register
+    uint8_t IMR;
+
+    bool edgeTriggered;
+    bool cascadeMode;
+    bool expectICW4;
+    bool readIRR;
+    int initControlWord;
+
   public:
     typedef I8259Params Params;
 
@@ -55,6 +68,8 @@ class I8259 : public BasicPioDevice
     I8259(Params * p) : BasicPioDevice(p)
     {
         pioSize = 2;
+        initControlWord = 0;
+        readIRR = true;
         latency = p->pio_latency;
         master = p->master;
     }