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authorRon Dreslinski <rdreslin@umich.edu>2006-10-09 19:15:24 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-09 19:15:24 -0400
commite03b9c9939d7782198c023b23ed33cde131f48c5 (patch)
treeec31e6bb7d4d0122d0996df37c81b44ec193dc9f /src
parent13ac9a419dcf2e1e0335bc65b20837e538a9beee (diff)
downloadgem5-e03b9c9939d7782198c023b23ed33cde131f48c5.tar.xz
Fix how upgrades work.
Remove some dead code. src/mem/cache/cache_impl.hh: Upgrades don't need a response. Moved satisfied check into bus so removed some dead code. src/mem/cache/coherence/coherence_protocol.cc: src/mem/packet.hh: Upgrades don't require a response --HG-- extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/cache_impl.hh8
-rw-r--r--src/mem/cache/coherence/coherence_protocol.cc2
-rw-r--r--src/mem/packet.hh3
3 files changed, 5 insertions, 8 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index af12b9255..c3c1c0881 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -63,9 +63,8 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
if (pkt->isWrite() && (pkt->req->isLocked())) {
pkt->req->setScResult(1);
}
- if (!(pkt->flags & SATISFIED)) {
- access(pkt);
- }
+ access(pkt);
+
}
else
{
@@ -204,9 +203,8 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
pkt->getAddr() & (((ULL(1))<<48)-1),
pkt->getAddr() & ~((Addr)blkSize - 1));
- //@todo Should this return latency have the hit latency in it?
-// respond(pkt,curTick+lat);
pkt->flags |= SATISFIED;
+ //Invalidates/Upgrades need no response if they get the bus
// return MA_HIT; //@todo, return values
return true;
}
diff --git a/src/mem/cache/coherence/coherence_protocol.cc b/src/mem/cache/coherence/coherence_protocol.cc
index bcf3ce9c5..e28dda3dc 100644
--- a/src/mem/cache/coherence/coherence_protocol.cc
+++ b/src/mem/cache/coherence/coherence_protocol.cc
@@ -271,7 +271,7 @@ CoherenceProtocol::CoherenceProtocol(const string &name,
}
Packet::Command writeToSharedCmd = doUpgrades ? Packet::UpgradeReq : Packet::ReadExReq;
- Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeResp : Packet::ReadExResp;
+ Packet::Command writeToSharedResp = doUpgrades ? Packet::UpgradeReq : Packet::ReadExResp;
//@todo add in hardware prefetch to this list
if (protocol == "msi") {
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index be9bf5f57..9d37fe157 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -194,8 +194,7 @@ class Packet
HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse,
InvalidateReq = IsInvalidate | IsRequest,
WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
- UpgradeReq = IsInvalidate | IsRequest | NeedsResponse,
- UpgradeResp = IsInvalidate | IsResponse | NeedsResponse,
+ UpgradeReq = IsInvalidate | IsRequest
ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse
};