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| author | Isaac Richter <isaac.richter@rochester.edu> | 2018-03-30 10:01:11 -0400 |
|---|---|---|
| committer | Jason Lowe-Power <jason@lowepower.com> | 2019-10-15 16:02:46 +0000 |
| commit | e71a1049e865faeccb949ec4c777540c4ac5fdff (patch) | |
| tree | 7ccac38976eeaf5e683d1a4d60046774b65c3ca9 /src | |
| parent | 008ae4b0650d9249ec719985eb5aa0726d643ed0 (diff) | |
| download | gem5-e71a1049e865faeccb949ec4c777540c4ac5fdff.tar.xz | |
arch-x86: Make LFENCE a serializing instruction
According to the Intel SDM, no instruction following an LFENCE can begin
execution until after the LFENCE has executed. (This is
less strict than an actual serializing instruction, such as CPUID.)
Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure
that no future instruction is fetched until after the serializing
instruction is completed.
By contrast, LFENCE (and other memory-ordering instructions) allows
future instructions to have been fetched; it just prohibits them from
being executed.
Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7
Signed-off-by: Isaac Richter <isaac.richter@rochester.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index dfb748efb..1e0924382 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -785,7 +785,8 @@ 0x6: decode MODRM_MOD { 0x3: decode MODRM_REG { 0x5: BasicOperate::LFENCE( - {{/*Nothing*/}}, IsReadBarrier); + {{/*Nothing*/}}, IsReadBarrier, + IsSerializeAfter); 0x6: BasicOperate::MFENCE( {{/*Nothing*/}}, IsMemBarrier); 0x7: BasicOperate::SFENCE( |