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authorAndreas Hansson <andreas.hansson@arm.com>2012-07-12 12:56:13 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-07-12 12:56:13 -0400
commitf00cba34eb8e6bf947721f72de314f4e8bd6a8f8 (patch)
tree432ab17d82d72d5042758f25066dc64558c9a7f8 /src
parent55bfe13705a3eccdffb6846dd87df5f190b04c99 (diff)
downloadgem5-f00cba34eb8e6bf947721f72de314f4e8bd6a8f8.tar.xz
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses.
Diffstat (limited to 'src')
-rw-r--r--src/mem/SimpleMemory.py2
-rw-r--r--src/mem/simple_mem.cc29
-rw-r--r--src/mem/simple_mem.hh9
3 files changed, 13 insertions, 27 deletions
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 51de3374d..c47d04222 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -44,6 +44,6 @@ from AbstractMemory import *
class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
- port = VectorSlavePort("Slave ports")
+ port = SlavePort("Slave ports")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index aa9168bf7..b9db64276 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -49,24 +49,17 @@ using namespace std;
SimpleMemory::SimpleMemory(const Params* p) :
AbstractMemory(p),
- lat(p->latency), lat_var(p->latency_var)
+ port(name() + ".port", *this), lat(p->latency), lat_var(p->latency_var)
{
- for (size_t i = 0; i < p->port_port_connection_count; ++i) {
- ports.push_back(new MemoryPort(csprintf("%s-port-%d", name(), i),
- *this));
- }
}
void
SimpleMemory::init()
{
- for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
- ++p) {
- if (!(*p)->isConnected()) {
- fatal("SimpleMemory port %s is unconnected!\n", (*p)->name());
- } else {
- (*p)->sendRangeChange();
- }
+ // allow unconnected memories as this is used in several ruby
+ // systems at the moment
+ if (port.isConnected()) {
+ port.sendRangeChange();
}
}
@@ -102,22 +95,14 @@ SimpleMemory::getSlavePort(const std::string &if_name, int idx)
if (if_name != "port") {
return MemObject::getSlavePort(if_name, idx);
} else {
- if (idx >= static_cast<int>(ports.size())) {
- fatal("SimpleMemory::getSlavePort: unknown index %d\n", idx);
- }
-
- return *ports[idx];
+ return port;
}
}
unsigned int
SimpleMemory::drain(Event *de)
{
- int count = 0;
- for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
- ++p) {
- count += (*p)->drain(de);
- }
+ int count = port.drain(de);
if (count)
changeState(Draining);
diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index 5f136ed51..95bfa57ad 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -54,9 +54,10 @@
#include "params/SimpleMemory.hh"
/**
- * The simple memory is a basic multi-ported memory with an infinite
- * throughput and a fixed latency, potentially with a variance added
- * to it. It uses a SimpleTimingPort to implement the timing accesses.
+ * The simple memory is a basic single-ported memory controller with
+ * an infinite throughput and a fixed latency, potentially with a
+ * variance added to it. It uses a SimpleTimingPort to implement the
+ * timing accesses.
*/
class SimpleMemory : public AbstractMemory
{
@@ -81,7 +82,7 @@ class SimpleMemory : public AbstractMemory
};
- std::vector<MemoryPort*> ports;
+ MemoryPort port;
Tick lat;
Tick lat_var;