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authorSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:20 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2016-02-06 17:21:20 -0800
commitf5343df1e1999e66c39b95085b77b547e7d94262 (patch)
tree87c16b2fd80e22d4402833604182bd3f72411464 /src
parent92b750d5efb56359e3c95ca6bc093ab4b6395aa1 (diff)
downloadgem5-f5343df1e1999e66c39b95085b77b547e7d94262.tar.xz
arch: get rid of dummy var init
MemOperand variables were being initialized to 0 "to avoid 'uninitialized variable' errors" but these no longer seem to be a problem (with the exception of one use case in POWER that is arguably broken and easily fixed here). Getting rid of the initialization is necessary to set up a subsequent patch which extends memory operands to possibly not be scalars, making the '= 0' initialization no longer feasible.
Diffstat (limited to 'src')
-rwxr-xr-xsrc/arch/isa_parser.py4
-rw-r--r--src/arch/power/isa/decoder.isa2
2 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 20df0a7db..cbc8651d1 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -790,10 +790,8 @@ class MemOperand(Operand):
return ''
def makeDecl(self):
- # Note that initializations in the declarations are solely
- # to avoid 'uninitialized variable' errors from the compiler.
# Declare memory data variable.
- return '%s %s = 0;\n' % (self.ctype, self.base_name)
+ return '%s %s;\n' % (self.ctype, self.base_name)
def makeRead(self, predRead):
if self.read_code != None:
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 11d222390..30002fe33 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -309,10 +309,10 @@ decode OPCODE default Unknown::unknown() {
151: stwx({{ Mem = Rs; }});
150: stwcx({{
bool store_performed = false;
+ Mem = Rs;
if (Rsv) {
if (RsvLen == 4) {
if (RsvAddr == EA) {
- Mem = Rs;
store_performed = true;
}
}