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authorNilay Vaish <nilay@cs.wisc.edu>2013-12-20 20:34:04 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-12-20 20:34:04 -0600
commitfc53f9ffcc880a5429fb41a881bc095bf200e4a4 (patch)
tree398d012bd772b37673e3046aad5ca3d48e872ec4 /src
parent30b259a31eb8e2b4dc5aaef2705ee3896a457062 (diff)
downloadgem5-fc53f9ffcc880a5429fb41a881bc095bf200e4a4.tar.xz
ruby: slicc: replace max_in_port_rank with number of inports
This patch replaces max_in_port_rank with the number of inports. The use of max_in_port_rank was causing spurious re-builds and incorrect initialization of variables in ruby related regression tests. This was due to the variable value being used across threads while compiling when it was not meant to be. Since the number of inports is state machine specific value, this problem should get solved.
Diffstat (limited to 'src')
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc8
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh4
-rw-r--r--src/mem/slicc/ast/InPortDeclAST.py8
-rw-r--r--src/mem/slicc/symbols/StateMachine.py12
4 files changed, 10 insertions, 22 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 2e4109c01..26cf91e9f 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -104,10 +104,10 @@ AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
{
if (m_waiting_buffers.count(addr) == 0) {
MsgVecType* msgVec = new MsgVecType;
- msgVec->resize(m_max_in_port_rank, NULL);
+ msgVec->resize(m_in_ports, NULL);
m_waiting_buffers[addr] = msgVec;
}
- (*(m_waiting_buffers[addr]))[m_cur_in_port_rank] = buf;
+ (*(m_waiting_buffers[addr]))[m_cur_in_port] = buf;
}
void
@@ -118,7 +118,7 @@ AbstractController::wakeUpBuffers(Address addr)
// Wake up all possible lower rank (i.e. lower priority) buffers that could
// be waiting on this message.
//
- for (int in_port_rank = m_cur_in_port_rank - 1;
+ for (int in_port_rank = m_cur_in_port - 1;
in_port_rank >= 0;
in_port_rank--) {
if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
@@ -138,7 +138,7 @@ AbstractController::wakeUpAllBuffers(Address addr)
// Wake up all possible lower rank (i.e. lower priority) buffers that could
// be waiting on this message.
//
- for (int in_port_rank = m_max_in_port_rank - 1;
+ for (int in_port_rank = m_in_ports - 1;
in_port_rank >= 0;
in_port_rank--) {
if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 3ad1a0fba..3bf331c62 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -145,8 +145,8 @@ class AbstractController : public ClockedObject, public Consumer
typedef std::vector<MessageBuffer*> MsgVecType;
typedef std::map< Address, MsgVecType* > WaitingBufType;
WaitingBufType m_waiting_buffers;
- int m_max_in_port_rank;
- int m_cur_in_port_rank;
+ unsigned int m_in_ports;
+ unsigned int m_cur_in_port;
int m_number_of_TBEs;
//! Map from physical network number to the Message Buffer.
diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
index c88d353d3..75f917f9a 100644
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -30,8 +30,6 @@ from slicc.ast.TypeAST import TypeAST
from slicc.symbols import Func, Type, Var
class InPortDeclAST(DeclAST):
- max_port_rank = 0
-
def __init__(self, slicc, ident, msg_type, var_expr, pairs, statements):
super(InPortDeclAST, self).__init__(slicc, pairs)
@@ -40,9 +38,6 @@ class InPortDeclAST(DeclAST):
self.var_expr = var_expr
self.statements = statements
self.queue_type = TypeAST(slicc, "InPort")
- if self.pairs.has_key("rank"):
- InPortDeclAST.max_port_rank = max(self.pairs["rank"],
- InPortDeclAST.max_port_rank)
def __repr__(self):
return "[InPortDecl: %s]" % self.ident
@@ -120,6 +115,3 @@ class InPortDeclAST(DeclAST):
# Add port to state machine
machine.addInPort(in_port)
-
- # Include max_rank to be used by StateMachine.py
- in_port["max_port_rank"] = InPortDeclAST.max_port_rank
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index c96af4a90..b969d79a3 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -460,12 +460,8 @@ $c_ident::$c_ident(const Params *p)
{
m_name = "${ident}";
''')
- #
- # max_port_rank is used to size vectors and thus should be one plus the
- # largest port rank
- #
- max_port_rank = self.in_ports[0].pairs["max_port_rank"] + 1
- code(' m_max_in_port_rank = $max_port_rank;')
+ num_in_ports = len(self.in_ports)
+ code(' m_in_ports = $num_in_ports;')
code.indent()
#
@@ -1104,9 +1100,9 @@ ${ident}_Controller::wakeup()
code.indent()
code('// ${ident}InPort $port')
if port.pairs.has_key("rank"):
- code('m_cur_in_port_rank = ${{port.pairs["rank"]}};')
+ code('m_cur_in_port = ${{port.pairs["rank"]}};')
else:
- code('m_cur_in_port_rank = 0;')
+ code('m_cur_in_port = 0;')
code('${{port["c_code_in_port"]}}')
code.dedent()