ARM: Eliminate decoding for the very deprecated FPA instructions.

4 files changed, 14 insertions, 265 deletions

diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 714b8bb7e..6c2db2026 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -1,4 +1,17 @@
-/* Copyright (c) 2007-2008 The Florida State University
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2007-2008 The Florida State University
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -102,71 +115,6 @@ class ArmMacroMemoryOp : public PredMacroOp
         microOps = new StaticInstPtr[numMicroops];
     }
 };
-
-/**
- * Arm Macro FPA operations to fix ldfd and stfd instructions
- */
-class ArmMacroFPAOp : public PredMacroOp
-{
-  protected:
-    uint32_t puswl,
-             prepost,
-             up,
-             psruser,
-             writeback,
-             loadop;
-    int32_t disp8;
-
-    ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-        : PredMacroOp(mnem, _machInst, __opClass),
-                      puswl(machInst.puswl),
-                      prepost(machInst.puswl.prepost),
-                      up(machInst.puswl.up),
-                      psruser(machInst.puswl.psruser),
-                      writeback(machInst.puswl.writeback),
-                      loadop(machInst.puswl.loadOp),
-                      disp8(machInst.immed7_0 << 2)
-    {
-        numMicroops = 3 + writeback;
-        microOps = new StaticInstPtr[numMicroops];
-    }
-};
-
-/**
- * Arm Macro FM operations to fix lfm and sfm
- */
-class ArmMacroFMOp : public PredMacroOp
-{
-  protected:
-    uint32_t punwl,
-             prepost,
-             up,
-             n1bit,
-             writeback,
-             loadop,
-             n0bit,
-             count;
-    int32_t disp8;
-
-    ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
-        : PredMacroOp(mnem, _machInst, __opClass),
-                      punwl(machInst.punwl),
-                      prepost(machInst.puswl.prepost),
-                      up(machInst.puswl.up),
-                      n1bit(machInst.opcode22),
-                      writeback(machInst.puswl.writeback),
-                      loadop(machInst.puswl.loadOp),
-                      n0bit(machInst.opcode15),
-                      disp8(machInst.immed7_0 << 2)
-    {
-        // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4)
-        count = (n1bit << 1) | n0bit;
-        if (count == 0)
-            count = 4;
-        numMicroops = (3*count) + writeback;
-        microOps = new StaticInstPtr[numMicroops];
-    }
-};
 }
 
 #endif //__ARCH_ARM_INSTS_MACROMEM_HH__
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 1154bd0ba..dcdce6ca2 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -314,71 +314,6 @@ format DataOp {
         1: Branch::bl({{ }}, Link);
     }
     0x6: decode CPNUM {
-        0x1: decode PUNWL {
-            0x02,0x0a: decode OPCODE_15 {
-                0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
-                                            Rn = Rn + disp8; }},
-                    {{ EA = Rn; }});
-                1: ArmMacroFPAOp::stfd_({{ }});
-            }
-            0x03,0x0b: decode OPCODE_15 {
-                0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
-                                           Rn = Rn + disp8; }},
-                    {{ EA = Rn; }});
-                1: ArmMacroFPAOp::ldfd_({{ }});
-            }
-            0x06,0x0e: decode OPCODE_15 {
-                0: ArmMacroFPAOp::stfe_nw({{ }});
-            }
-            0x07,0x0f: decode OPCODE_15 {
-                0: ArmMacroFPAOp::ldfe_nw({{ }});
-            }
-            0x10,0x18: decode OPCODE_15 {
-                0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::stfd_p({{ }});
-            }
-            0x11,0x19: decode OPCODE_15 {
-                0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::ldfd_p({{ }});
-            }
-            0x12,0x1a: decode OPCODE_15 {
-                0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
-                                              Rn = Rn + disp8; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::stfd_pw({{ }});
-            }
-            0x13,0x1b: decode OPCODE_15 {
-                0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
-                                             Rn = Rn + disp8; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::ldfd_pw({{ }});
-            }
-            0x14,0x1c: decode OPCODE_15 {
-                0: ArmMacroFPAOp::stfe_pn({{ }});
-            }
-            0x15,0x1d: decode OPCODE_15 {
-                0: ArmMacroFPAOp::ldfe_pn({{ }});
-            }
-            0x16,0x1e: decode OPCODE_15 {
-                0: ArmMacroFPAOp::stfe_pnw({{ }});
-            }
-            0x17,0x1f: decode OPCODE_15 {
-                0: ArmMacroFPAOp::ldfe_pnw({{ }});
-            }
-        }
-        0x2: decode PUNWL {
-            // could really just decode as a single instruction
-            0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
-            0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
-            0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
-            0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
-            0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
-            0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
-            0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
-            0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
-        }
         0xb: decode LOADOP {
             0x0: WarnUnimpl::fstmx();
             0x1: WarnUnimpl::fldmx();
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa
index c834c22cb..704e4b71a 100644
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -147,33 +147,6 @@ let {{
 
 ////////////////////////////////////////////////////////////////////
 //
-// Moving to/from double floating point registers
-//
-
-let {{
-    microMvtdUopIop = InstObjParams('mvtd_uop', 'MicroMvtdUop',
-                                    'PredOp',
-                                    {'code': 'Fd.ud = (Rhi.ud << 32) | Rlo;',
-                                     'predicate_test': predicateTest},
-                                    ['IsMicroop'])
-
-    microMvfdUopIop = InstObjParams('mvfd_uop', 'MicroMvfdUop',
-                                    'PredOp',
-                                    {'code': '''Rhi = bits(Fd.ud, 63, 32);
-                                                Rlo = bits(Fd.ud, 31, 0);''',
-                                     'predicate_test': predicateTest},
-                                    ['IsMicroop'])
-
-    header_output = BasicDeclare.subst(microMvtdUopIop) + \
-                    BasicDeclare.subst(microMvfdUopIop)
-    decoder_output = BasicConstructor.subst(microMvtdUopIop) + \
-                     BasicConstructor.subst(microMvfdUopIop)
-    exec_output = PredOpExecute.subst(microMvtdUopIop) + \
-                  PredOpExecute.subst(microMvfdUopIop)
-}};
-
-////////////////////////////////////////////////////////////////////
-//
 // Macro Memory-format instructions
 //
 
@@ -275,67 +248,6 @@ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *trace
 }
 }};
 
-def template MacroFPAConstructor {{
-inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
-    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
-{
-    %(constructor)s;
-
-    uint32_t start_addr = 0;
-
-    if (prepost)
-        start_addr = disp8;
-    else
-        start_addr = 0;
-
-    emit_ldfstf_uops(microOps, 0, machInst, loadop, up, start_addr);
-
-    if (writeback)
-    {
-        if (up) {
-            microOps[numMicroops - 1] =
-                new MicroAddiUop(machInst, RN, RN, disp8);
-        } else {
-            microOps[numMicroops - 1] =
-                new MicroSubiUop(machInst, RN, RN, disp8);
-        }
-    }
-    microOps[numMicroops - 1]->setLastMicroop();
-}
-
-}};
-
-
-def template MacroFMConstructor {{
-inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
-    : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
-{
-    %(constructor)s;
-
-    uint32_t start_addr = 0;
-
-    if (prepost)
-        start_addr = disp8;
-    else
-        start_addr = 0;
-
-    for (int i = 0; i < count; i++)
-        emit_ldfstf_uops(microOps, 3*i, machInst, loadop, up, start_addr);
-
-    if (writeback) {
-        if (up) {
-            microOps[numMicroops - 1] =
-                new MicroAddiUop(machInst, RN, RN, disp8);
-        } else {
-            microOps[numMicroops - 1] =
-                new MicroSubiUop(machInst, RN, RN, disp8);
-        }
-    }
-    microOps[numMicroops - 1]->setLastMicroop();
-}
-}};
-
-
 def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
     iop = InstObjParams(name, Name, 'ArmMacroMemoryOp', code, opt_flags)
     header_output = MacroStoreDeclare.subst(iop)
@@ -343,25 +255,3 @@ def format ArmMacroStore(code, mem_flags = [], inst_flag = [], *opt_flags) {{
     decode_block = BasicDecode.subst(iop)
     exec_output = MacroStoreExecute.subst(iop)
 }};
-
-def format ArmMacroFPAOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
-    iop = InstObjParams(name, Name, 'ArmMacroFPAOp',
-                        {"code": code,
-                         "predicate_test": predicateTest},
-                        opt_flags)
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = MacroFPAConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = PredOpExecute.subst(iop)
-}};
-
-def format ArmMacroFMOp(code, mem_flags = [], inst_flag = [], *opt_flags) {{
-    iop = InstObjParams(name, Name, 'ArmMacroFMOp',
-                        {"code": code,
-                         "predicate_test": predicateTest},
-                        opt_flags)
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = MacroFMConstructor.subst(iop)
-    decode_block = BasicDecode.subst(iop)
-    exec_output = PredOpExecute.subst(iop)
-}};
diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa
index d42ffb147..d4dd41d2b 100644
--- a/src/arch/arm/isa/formats/util.isa
+++ b/src/arch/arm/isa/formats/util.isa
@@ -79,8 +79,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
 
 output header {{
         std::string inst2string(MachInst machInst);
-        StaticInstPtr gen_ldrstr_uop(uint32_t baseinst, int loadop, uint32_t rd, int32_t disp);
-        int emit_ldfstf_uops(StaticInstPtr* microOps, int index, uint32_t baseinst, int loadop, int up, int32_t disp);
 }};
 
 output decoder {{
@@ -102,28 +100,6 @@ output decoder {{
 
         return str;
     }
-
-    // Emits uops for a double fp move
-    void
-    emit_ldfstf_uops(StaticInstPtr* microOps, int index, ExtMachInst machInst,
-                     bool loadop, bool up, int32_t disp)
-    {
-        if (loadop)
-        {
-            microOps[index++] = new MicroLdrUop(machInst, 19, RN, disp);
-            microOps[index++] =
-                new MicroLdrUop(machInst, 18, RN, disp + (up ? 4 : -4));
-            microOps[index++] = new MicroMvtdUop(machInst);
-        }
-        else
-        {
-            microOps[index++] = new MicroMvfdUop(machInst);
-            microOps[index++] = new MicroStrUop(machInst, 19, RN, disp);
-            microOps[index++] =
-                new MicroStrUop(machInst, 18, RN, disp + (up ? 4 : -4));
-        }
-    }
-
 }};