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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-13 13:55:36 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-02-20 13:30:02 +0000
commit26b03914d7dbcf6b6c8c0a9c08d4e3ff81365376 (patch)
tree67bfd89bd42b5d6fcc9c9dd15e7f6541522dc031 /src
parenta7083ece990adddfd3bec8b48c5db7dee1781d55 (diff)
downloadgem5-26b03914d7dbcf6b6c8c0a9c08d4e3ff81365376.tar.xz
arch-arm: Add AArch32 SVC Semihosting interface
AArch32 Svc instruction is now able to issue Arm Semihosting commands as the AArch64 counterpart in either Arm and Thumb mode. Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8371 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/insts/misc.isa19
1 files changed, 15 insertions, 4 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index cf3d0e00f..566ea4b9d 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,15 +40,26 @@
let {{
svcCode = '''
- fault = std::make_shared<SupervisorCall>(machInst, imm);
+ ThreadContext *tc = xc->tcBase();
+
+ const auto semihost_imm = Thumb? 0xAB : 0x123456;
+
+ if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
+ R0 = ArmSystem::callSemihosting32(tc, R0, R1);
+ } else {
+ fault = std::make_shared<SupervisorCall>(machInst, imm);
+ }
'''
svcIop = InstObjParams("svc", "Svc", "ImmOp",
{ "code": svcCode,
- "predicate_test": predicateTest },
- ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
+ "predicate_test": predicateTest,
+ "thumb_semihost": '0xAB',
+ "arm_semihost": '0x123456' },
+ ["IsSyscall", "IsNonSpeculative",
+ "IsSerializeAfter"])
header_output = ImmOpDeclare.subst(svcIop)
- decoder_output = ImmOpConstructor.subst(svcIop)
+ decoder_output = SemihostConstructor.subst(svcIop)
exec_output = PredOpExecute.subst(svcIop)
smcCode = '''