sim: Add the notion of clock domains to all ClockedObjects

This patch adds the notion of source- and derived-clock domains to the
ClockedObjects. As such, all clock information is moved to the clock
domain, and the ClockedObjects are grouped into domains.

The clock domains are either source domains, with a specific clock
period, or derived domains that have a parent domain and a divider
(potentially chained). For piece of logic that runs at a derived clock
(a ratio of the clock its parent is running at) the necessary derived
clock domain is created from its corresponding parent clock
domain. For now, the derived clock domain only supports a divider,
thus ensuring a lower speed compared to its parent. Multiplier
functionality implies a PLL logic that has not been modelled yet
(create a separate clock instead).

The clock domains should be used as a mechanism to provide a
controllable clock source that affects clock for every clocked object
lying beneath it. The clock of the domain can (in a future patch) be
controlled by a handler responsible for dynamic frequency scaling of
the respective clock domains.

All the config scripts have been retro-fitted with clock domains. For
the System a default SrcClockDomain is created. For CPUs that run at a
different speed than the system, there is a seperate clock domain
created. This domain incorporates the CPU and the associated
caches. As before, Ruby runs under its own clock domain.

The clock period of all domains are pre-computed, such that no virtual
functions or multiplications are needed when calling
clockPeriod. Instead, the clock period is pre-computed when any
changes occur. For this to be possible, each clock domain tracks its
children.

13 files changed, 376 insertions, 33 deletions

diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index 2486ec059..cc8e453b1 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -45,7 +45,7 @@ class LinuxAlphaSystem(AlphaSystem):
     system_type = 34
     system_rev = 1 << 10
 
-    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock.frequency,
                                          "boot processor frequency")
 
 class FreebsdAlphaSystem(AlphaSystem):
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index c6ceb71db..4605b21a7 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -50,7 +50,7 @@ class LinuxMipsSystem(MipsSystem):
     system_type = 34
     system_rev = 1 << 10
 
-    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock.frequency,
                                          "boot processor frequency")
 
 class BareIronMipsSystem(MipsSystem):
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index e7613c5bb..7ec79ad0a 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -52,6 +52,7 @@ from InstTracer import InstTracer
 from ExeTracer import ExeTracer
 from MemObject import MemObject
 from BranchPredictor import BranchPredictor
+from ClockDomain import *
 
 default_tracer = ExeTracer()
 
@@ -226,7 +227,10 @@ class BaseCPU(MemObject):
         elif buildEnv['TARGET_ISA'] == 'alpha':
             self.interrupts = AlphaInterrupts()
         elif buildEnv['TARGET_ISA'] == 'x86':
-            self.interrupts = X86LocalApic(clock = Parent.clock * 16,
+            self.apic_clk_domain = DerivedClockDomain(clk_domain =
+                                                      Parent.clk_domain,
+                                                      clk_divider = 16)
+            self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain,
                                            pio_addr=0x2000000000000000)
             _localApic = self.interrupts
         elif buildEnv['TARGET_ISA'] == 'mips':
diff --git a/src/cpu/dummy_checker.cc b/src/cpu/dummy_checker.cc
index 7a5b46e43..bbd905492 100644
--- a/src/cpu/dummy_checker.cc
+++ b/src/cpu/dummy_checker.cc
@@ -54,7 +54,7 @@ DummyCheckerParams::create()
     params->max_insts_all_threads = 0;
     params->max_loads_any_thread = 0;
     params->max_loads_all_threads = 0;
-    params->clock = clock;
+    params->clk_domain = clk_domain;
     // Hack to touch all parameters.  Consider not deriving Checker
     // from BaseCPU..it's not really a CPU in the end.
     Counter temp;
diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc
index 3ff3d86bc..ce7a99f0f 100644
--- a/src/cpu/o3/checker.cc
+++ b/src/cpu/o3/checker.cc
@@ -66,7 +66,7 @@ O3CheckerParams::create()
     params->exitOnError = exitOnError;
     params->updateOnError = updateOnError;
     params->warnOnlyOnLoadError = warnOnlyOnLoadError;
-    params->clock = clock;
+    params->clk_domain = clk_domain;
     params->tracer = tracer;
     // Hack to touch all parameters.  Consider not deriving Checker
     // from BaseCPU..it's not really a CPU in the end.
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 0072b90fa..147ad156c 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -84,8 +84,6 @@ class IGbE(EtherDevice):
         "Number of enteries in the rx descriptor cache")
     tx_desc_cache_size = Param.Int(64,
         "Number of enteries in the rx descriptor cache")
-    # Override the default clock
-    clock = '500MHz'
     VendorID = 0x8086
     SubsystemID = 0x1008
     SubsystemVendorID = 0x8086
@@ -135,9 +133,6 @@ class EtherDevBase(EtherDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    # Override the default clock
-    clock = '500MHz'
-
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
     dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
diff --git a/src/mem/ruby/system/RubyMemoryControl.py b/src/mem/ruby/system/RubyMemoryControl.py
index e46b3f223..118e4f20e 100644
--- a/src/mem/ruby/system/RubyMemoryControl.py
+++ b/src/mem/ruby/system/RubyMemoryControl.py
@@ -37,8 +37,6 @@ class RubyMemoryControl(MemoryControl):
     cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
     version = Param.Int("");
 
-    # Override the default clock
-    clock = '400MHz'
     banks_per_rank = Param.Int(8, "");
     ranks_per_dimm = Param.Int(2, "");
     dimms_per_channel = Param.Int(2, "");
diff --git a/src/sim/ClockDomain.py b/src/sim/ClockDomain.py
new file mode 100644
index 000000000..37958dc26
--- /dev/null
+++ b/src/sim/ClockDomain.py
@@ -0,0 +1,60 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Vasileios Spiliopoulos
+#          Akash Bagdia
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+# Abstract clock domain
+class ClockDomain(SimObject):
+    type = 'ClockDomain'
+    cxx_header = "sim/clock_domain.hh"
+    abstract = True
+
+# Source clock domain with an actual clock
+class SrcClockDomain(ClockDomain):
+    type = 'SrcClockDomain'
+    cxx_header = "sim/clock_domain.hh"
+    clock = Param.Clock("Clock period")
+
+# Derived clock domain with a parent clock domain and a frequency
+# divider
+class DerivedClockDomain(ClockDomain):
+    type = 'DerivedClockDomain'
+    cxx_header = "sim/clock_domain.hh"
+    clk_domain = Param.ClockDomain("Parent clock domain")
+    clk_divider = Param.Unsigned(1, "Frequency divider")
diff --git a/src/sim/ClockedObject.py b/src/sim/ClockedObject.py
index 8bc4031a4..2562f1f01 100644
--- a/src/sim/ClockedObject.py
+++ b/src/sim/ClockedObject.py
@@ -44,7 +44,6 @@ class ClockedObject(SimObject):
     abstract = True
     cxx_header = "sim/clocked_object.hh"
 
-    # Clock period of this object, with the default value being the
-    # clock period of the parent object, unproxied at instantiation
-    # time
-    clock = Param.Clock(Parent.clock, "Clock speed")
+    # The clock domain this clocked object belongs to, inheriting the
+    # parent's clock domain by default
+    clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain")
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 093130f24..7aa4702cd 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -34,6 +34,7 @@ SimObject('BaseTLB.py')
 SimObject('ClockedObject.py')
 SimObject('Root.py')
 SimObject('InstTracer.py')
+SimObject('ClockDomain.py')
 
 Source('arguments.cc')
 Source('async.cc')
@@ -50,6 +51,7 @@ Source('sim_object.cc')
 Source('simulate.cc')
 Source('stat_control.cc')
 Source('syscall_emul.cc')
+Source('clock_domain.cc')
 
 if env['TARGET_ISA'] != 'no':
     SimObject('Process.py')
@@ -81,3 +83,4 @@ DebugFlag('Thread')
 DebugFlag('Timer')
 DebugFlag('VtoPhys')
 DebugFlag('WorkItems')
+DebugFlag('ClockDomain')
diff --git a/src/sim/clock_domain.cc b/src/sim/clock_domain.cc
new file mode 100644
index 000000000..262ae904c
--- /dev/null
+++ b/src/sim/clock_domain.cc
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Vasileios Spiliopoulos
+ *          Akash Bagdia
+ *          Andreas Hansson
+ */
+
+#include "debug/ClockDomain.hh"
+#include "params/ClockDomain.hh"
+#include "params/DerivedClockDomain.hh"
+#include "params/SrcClockDomain.hh"
+#include "sim/clock_domain.hh"
+
+SrcClockDomain::SrcClockDomain(const Params *p) : ClockDomain(p)
+{
+    clockPeriod(p->clock);
+}
+
+void
+SrcClockDomain::clockPeriod(Tick clock_period)
+{
+    if (clock_period == 0) {
+        fatal("%s has a clock period of zero\n", name());
+    }
+
+    _clockPeriod = clock_period;
+
+    DPRINTF(ClockDomain,
+            "Setting clock period to %d ticks for source clock %s\n",
+            _clockPeriod, name());
+
+    // inform any derived clocks they need to updated their period
+    for (auto c = children.begin(); c != children.end(); ++c) {
+        (*c)->updateClockPeriod();
+    }
+}
+
+SrcClockDomain *
+SrcClockDomainParams::create()
+{
+    return new SrcClockDomain(this);
+}
+
+DerivedClockDomain::DerivedClockDomain(const Params *p) :
+    ClockDomain(p),
+    parent(*p->clk_domain),
+    clockDivider(p->clk_divider)
+{
+    // Ensure that clock divider setting works as frequency divider and never
+    // work as frequency multiplier
+    if (clockDivider < 1) {
+       fatal("Clock divider param cannot be less than 1");
+    }
+
+    // let the parent keep track of this derived domain so that it can
+    // propagate changes
+    parent.addDerivedDomain(this);
+
+    // update our clock period based on the parents clock
+    updateClockPeriod();
+}
+
+void
+DerivedClockDomain::updateClockPeriod()
+{
+    // recalculate the clock period, relying on the fact that changes
+    // propagate downwards in the tree
+    _clockPeriod = parent.clockPeriod() * clockDivider;
+
+    DPRINTF(ClockDomain,
+            "Setting clock period to %d ticks for derived clock %s\n",
+            _clockPeriod, name());
+
+    // inform any derived clocks
+    for (auto c = children.begin(); c != children.end(); ++c) {
+        (*c)->updateClockPeriod();
+    }
+}
+
+DerivedClockDomain *
+DerivedClockDomainParams::create()
+{
+    return new DerivedClockDomain(this);
+}
diff --git a/src/sim/clock_domain.hh b/src/sim/clock_domain.hh
new file mode 100644
index 000000000..c3f53e675
--- /dev/null
+++ b/src/sim/clock_domain.hh
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Vasileios Spiliopoulos
+ *          Akash Bagdia
+ */
+
+/**
+ * @file
+ * ClockDomain declarations.
+ */
+
+#ifndef __SIM_CLOCK_DOMAIN_HH__
+#define __SIM_CLOCK_DOMAIN_HH__
+
+#include "base/statistics.hh"
+#include "params/ClockDomain.hh"
+#include "params/DerivedClockDomain.hh"
+#include "params/SrcClockDomain.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * Forward declaration
+ */
+class DerivedClockDomain;
+
+/**
+ * The ClockDomain provides clock to group of clocked objects bundled
+ * under the same clock domain. The clock domains provide support for
+ * a hierarchial structure with source and derived domains.
+ */
+class ClockDomain : public SimObject
+{
+
+  protected:
+
+    /**
+     * Pre-computed clock period in ticks. This is populated by the
+     * inheriting classes based on how their period is determined.
+     */
+    Tick _clockPeriod;
+
+    /**
+     * Pointers to potential derived clock domains so we can propagate
+     * changes.
+     */
+    std::vector<DerivedClockDomain*> children;
+
+  public:
+
+    typedef ClockDomainParams Params;
+    ClockDomain(const Params *p) : SimObject(p), _clockPeriod(0) {}
+
+    /**
+     * Get the clock period.
+     *
+     * @return Clock period in ticks
+     */
+    inline Tick clockPeriod() const { return _clockPeriod; }
+
+    /**
+     * Add a derived domain.
+     *
+     * @param Derived domain to add as a child
+     */
+    void addDerivedDomain(DerivedClockDomain *clock_domain)
+    { children.push_back(clock_domain); }
+
+};
+
+/**
+ * The source clock domains provides the notion of a clock domain that is
+ * connected to a tunable clock source. It maintains the clock period and
+ * provides methods for setting/getting the clock.
+ */
+class SrcClockDomain : public ClockDomain
+{
+
+  public:
+
+    typedef SrcClockDomainParams Params;
+    SrcClockDomain(const Params *p);
+
+    /**
+     * Set new clock value
+     * @param clock The new clock period in ticks
+     */
+    void clockPeriod(Tick clock_period);
+
+};
+
+/**
+ * The derived clock domains provides the notion of a clock domain
+ * that is connected to a parent clock domain that can either be a
+ * source clock domain or a derived clock domain. It maintains the
+ * clock divider and provides methods for getting the clock.
+ */
+class DerivedClockDomain: public ClockDomain
+{
+
+  public:
+
+    typedef DerivedClockDomainParams Params;
+    DerivedClockDomain(const Params *p);
+
+    /**
+     * Called by the parent clock domain to propagate changes. This
+     * also involves propagating the change further to any children of
+     * the derived domain itself.
+     */
+    void updateClockPeriod();
+
+  private:
+
+    /**
+     * Reference to the parent clock domain this clock domain derives
+     * its clock period from
+     */
+    ClockDomain &parent;
+
+    /**
+     * Local clock divider of the domain
+     */
+    const uint64_t clockDivider;
+};
+
+#endif
diff --git a/src/sim/clocked_object.hh b/src/sim/clocked_object.hh
index d836c48cc..c959c5c04 100644
--- a/src/sim/clocked_object.hh
+++ b/src/sim/clocked_object.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -49,6 +49,7 @@
 #include "base/misc.hh"
 #include "params/ClockedObject.hh"
 #include "sim/core.hh"
+#include "sim/clock_domain.hh"
 #include "sim/sim_object.hh"
 
 /**
@@ -88,7 +89,7 @@ class ClockedObject : public SimObject
 
         // optimise for the common case and see if the tick should be
         // advanced by a single clock period
-        tick += clock;
+        tick += clockPeriod();
         ++cycle;
 
         // see if we are done at this point
@@ -98,26 +99,25 @@ class ClockedObject : public SimObject
         // if not, we have to recalculate the cycle and tick, we
         // perform the calculations in terms of relative cycles to
         // allow changes to the clock period in the future
-        Cycles elapsedCycles(divCeil(curTick() - tick, clock));
+        Cycles elapsedCycles(divCeil(curTick() - tick, clockPeriod()));
         cycle += elapsedCycles;
-        tick += elapsedCycles * clock;
+        tick += elapsedCycles * clockPeriod();
     }
 
-    // Clock period in ticks
-    Tick clock;
+    /**
+     * The clock domain this clocked object belongs to
+     */
+    ClockDomain &clockDomain;
 
   protected:
 
     /**
-     * Create a clocked object and set the clock based on the
+     * Create a clocked object and set the clock domain based on the
      * parameters.
      */
     ClockedObject(const ClockedObjectParams* p) :
-        SimObject(p), tick(0), cycle(0), clock(p->clock)
+        SimObject(p), tick(0), cycle(0), clockDomain(*p->clk_domain)
     {
-        if (clock == 0) {
-            fatal("%s has a clock period of zero\n", name());
-        }
     }
 
     /**
@@ -132,9 +132,9 @@ class ClockedObject : public SimObject
      */
     void resetClock() const
     {
-        Cycles elapsedCycles(divCeil(curTick(), clock));
+        Cycles elapsedCycles(divCeil(curTick(), clockPeriod()));
         cycle = elapsedCycles;
-        tick = elapsedCycles * clock;
+        tick = elapsedCycles * clockPeriod();
     }
 
   public:
@@ -154,7 +154,7 @@ class ClockedObject : public SimObject
         update();
 
         // figure out when this future cycle is
-        return tick + clock * cycles;
+        return tick + clockPeriod() * cycles;
     }
 
     /**
@@ -181,12 +181,18 @@ class ClockedObject : public SimObject
     Tick nextCycle() const
     { return clockEdge(Cycles(1)); }
 
-    inline uint64_t frequency() const { return SimClock::Frequency / clock; }
+    inline uint64_t frequency() const
+    {
+        return SimClock::Frequency / clockPeriod();
+    }
 
-    inline Tick clockPeriod() const { return clock; }
+    inline Tick clockPeriod() const
+    {
+        return clockDomain.clockPeriod();
+    }
 
     inline Cycles ticksToCycles(Tick t) const
-    { return Cycles(t / clock); }
+    { return Cycles(t / clockPeriod()); }
 
 };