Mem: Eliminate the NO_FAULT request flag.

8 files changed, 26 insertions, 10 deletions

diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index e93e16711..ff6de8d03 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -144,7 +144,7 @@ DtbFault::invoke(ThreadContext *tc)
     // read, like the EV5).  The EV6 approach is cleaner and seems to
     // work with EV5 PAL code, but not the other way around.
     if (!tc->misspeculating() &&
-        reqFlags.noneSet(Request::VPTE|Request::NO_FAULT)) {
+        reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
         // set VA register with faulting address
         tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index cb43fcb74..52e124ad5 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -627,7 +627,7 @@ decode OPCODE default Unknown::unknown() {
         format MiscPrefetch {
             0xf800: wh64({{ EA = Rb & ~ULL(63); }},
                          {{ xc->writeHint(EA, 64, memAccessFlags); }},
-                         mem_flags = NO_FAULT,
+                         mem_flags = PREFETCH,
                          inst_flags = [IsMemRef, IsDataPrefetch,
                                        IsStore, MemWriteOp]);
         }
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index fedfbf55d..b1703221f 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -548,7 +548,7 @@ def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
     pf_flags = makeList(pf_flags)
     inst_flags = makeList(inst_flags)
 
-    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+    pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
     pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
                                   'IsDataPrefetch', 'MemReadOp']
 
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index adcb16137..161a52b06 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -619,7 +619,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
 
 def format Prefetch(ea_code = {{ EA = Rs + disp; }},
                           mem_flags = [], pf_flags = [], inst_flags = []) {{
-    pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT']
+    pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
     pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad',
                                   'IsDataPrefetch', 'MemReadOp']
 
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 7dacc58ff..16b779e06 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -326,7 +326,7 @@ CheckerCPU::checkFlags(Request *req)
 {
     // Remove any dynamic flags that don't have to do with the request itself.
     unsigned flags = unverifiedReq->getFlags();
-    unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
+    unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | PREFETCH;
     flags = flags & (mask);
     if (flags == req->getFlags()) {
         return false;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index cd4f5457e..c092b5b1f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -353,8 +353,14 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
             recordEvent("Uncached Read");
 
         //If there's a fault, return it
-        if (fault != NoFault)
-            return fault;
+        if (fault != NoFault) {
+            if (req->isPrefetch()) {
+                return NoFault;
+            } else {
+                return fault;
+            }
+        }
+
         //If we don't need to access a second cache line, stop now.
         if (secondAddr <= addr)
         {
@@ -531,7 +537,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
                 assert(locked);
                 locked = false;
             }
-            return fault;
+            if (fault != NoFault && req->isPrefetch()) {
+                return NoFault;
+            } else {
+                return fault;
+            }
         }
 
         /*
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 8d3bae3f6..6b22d2fcf 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -273,6 +273,8 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
 {
     _status = Running;
     if (fault != NoFault) {
+        if (req->isPrefetch())
+            fault = NoFault;
         delete data;
         delete req;
 
@@ -315,6 +317,10 @@ TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
 {
     _status = Running;
     if (fault1 != NoFault || fault2 != NoFault) {
+        if (req1->isPrefetch())
+            fault1 = NoFault;
+        if (req2->isPrefetch())
+            fault2 = NoFault;
         delete data;
         delete req1;
         delete req2;
@@ -360,6 +366,8 @@ TimingSimpleCPU::sendSplitData(Fault fault1, Fault fault2,
 void
 TimingSimpleCPU::translationFault(Fault fault)
 {
+    // fault may be NoFault in cases where a fault is suppressed,
+    // for instance prefetches.
     numCycles += tickToCycles(curTick - previousTick);
     previousTick = curTick;
 
diff --git a/src/mem/request.hh b/src/mem/request.hh
index c8c31ffcd..f2cc4647c 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -72,8 +72,6 @@ class Request : public FastAlloc
     /** This request is to a memory mapped register. */
     static const FlagsType MMAPED_IPR                  = 0x00002000;
 
-    /** The request should not cause a page fault. */
-    static const FlagsType NO_FAULT                    = 0x00010000;
     /** The request should ignore unaligned access faults */
     static const FlagsType NO_ALIGN_FAULT              = 0x00020000;
     /** The request should ignore unaligned access faults */