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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-16 15:56:22 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-08-16 15:56:22 -0400 |
commit | ec0a18ffb956bbcf54b8d4d94dac7255f8868a9e (patch) | |
tree | 775a61f5d642b3d9a9a423995e9e046effb7243b /src | |
parent | 8a82553aec48029a7752f7192ca1c65236192cce (diff) | |
download | gem5-ec0a18ffb956bbcf54b8d4d94dac7255f8868a9e.tar.xz |
Fixes for Kevins O3 model to work with the blocking caches.
src/cpu/o3/fetch_impl.hh:
Fix ordering so dereference works
src/cpu/o3/lsq_impl.hh:
Check to make sure we didn't squash already
src/cpu/o3/lsq_unit.hh:
Fix for counting squashed retrys in the WB count
src/cpu/o3/lsq_unit_impl.hh:
Make sure to set retryID for stores, and clear it appropriately
--HG--
extra : convert_revision : 689765a1baea7b36f13eb177d65e97b52b6da09f
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/lsq_impl.hh | 5 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit.hh | 2 | ||||
-rw-r--r-- | src/cpu/o3/lsq_unit_impl.hh | 2 |
4 files changed, 10 insertions, 1 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 990db88ac..25be9d455 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -672,9 +672,9 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC, unsigned tid) assert(cacheBlocked); cacheBlocked = false; retryTid = -1; - retryPkt = NULL; delete retryPkt->req; delete retryPkt; + retryPkt = NULL; } fetchStatus[tid] = Squashing; diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index db2c253e1..2bbab71f0 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -71,6 +71,11 @@ template <class Impl> void LSQ<Impl>::DcachePort::recvRetry() { + if (lsq->retryTid == -1) + { + //Squashed, so drop it + return; + } lsq->thread[lsq->retryTid].recvRetry(); // Speculatively clear the retry Tid. This will get set again if // the LSQUnit was unable to complete its access. diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 512b5a63c..1358a3699 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -646,6 +646,8 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx) // handle it. if (lsq->cacheBlocked()) { ++lsqCacheBlocked; + + iewStage->decrWb(load_inst->seqNum); // There's an older load that's already going to squash. if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) return NoFault; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 4f5dbbf1c..fa716c712 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -626,6 +626,7 @@ LSQUnit<Impl>::writebackStores() ++lsqCacheBlocked; assert(retryPkt == NULL); retryPkt = data_pkt; + lsq->setRetryTid(lsqID); } else { storePostSend(data_pkt); } @@ -869,6 +870,7 @@ LSQUnit<Impl>::recvRetry() storePostSend(retryPkt); retryPkt = NULL; isStoreBlocked = false; + lsq->setRetryTid(-1); } else { // Still blocked! ++lsqCacheBlocked; |