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| author | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2009-05-12 15:01:14 -0400 |
| commit | f41df0ee08467711c613faadf9879052ab7196ed (patch) | |
| tree | b5ad5be9cecdec14d6f646e099edf9efcc8b38b0 /src | |
| parent | 5127ea226a0a2cd75334c5af4cb182a1fd9b6cf1 (diff) | |
| download | gem5-f41df0ee08467711c613faadf9879052ab7196ed.tar.xz | |
inorder-o3: allow both to compile together
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/2bit_local_pred.cc (renamed from src/cpu/o3/2bit_local_pred.cc) | 0 | ||||
| -rw-r--r-- | src/cpu/SConscript | 7 | ||||
| -rw-r--r-- | src/cpu/btb.cc (renamed from src/cpu/o3/btb.cc) | 0 | ||||
| -rw-r--r-- | src/cpu/inorder/SConscript | 5 | ||||
| -rwxr-xr-x | src/cpu/o3/SConscript | 6 | ||||
| -rw-r--r-- | src/cpu/ras.cc (renamed from src/cpu/o3/ras.cc) | 0 | ||||
| -rw-r--r-- | src/cpu/tournament_pred.cc (renamed from src/cpu/o3/tournament_pred.cc) | 0 |
7 files changed, 7 insertions, 11 deletions
diff --git a/src/cpu/o3/2bit_local_pred.cc b/src/cpu/2bit_local_pred.cc index 77a45ea26..77a45ea26 100644 --- a/src/cpu/o3/2bit_local_pred.cc +++ b/src/cpu/2bit_local_pred.cc diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 854db9f12..b14d606b7 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -128,6 +128,13 @@ Source('simple_thread.cc') Source('thread_context.cc') Source('thread_state.cc') +if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']: + Source('btb.cc') + Source('tournament_pred.cc') + Source('2bit_local_pred.cc') + Source('ras.cc') + TraceFlag('FreeList') + if env['FULL_SYSTEM']: SimObject('IntrControl.py') diff --git a/src/cpu/o3/btb.cc b/src/cpu/btb.cc index 93d6ee768..93d6ee768 100644 --- a/src/cpu/o3/btb.cc +++ b/src/cpu/btb.cc diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript index af237a777..9403aa914 100644 --- a/src/cpu/inorder/SConscript +++ b/src/cpu/inorder/SConscript @@ -35,7 +35,6 @@ if 'InOrderCPU' in env['CPU_MODELS']: SimObject('InOrderTrace.py') TraceFlag('ResReqCount') - TraceFlag('FreeList') TraceFlag('InOrderStage') TraceFlag('InOrderStall') TraceFlag('InOrderCPU') @@ -81,10 +80,6 @@ if 'InOrderCPU' in env['CPU_MODELS']: Source('resources/mult_div_unit.cc') Source('resource_pool.cc') Source('reg_dep_map.cc') - Source('../o3/btb.cc') - Source('../o3/tournament_pred.cc') - Source('../o3/2bit_local_pred.cc') - Source('../o3/ras.cc') Source('thread_context.cc') Source('cpu.cc') diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index f05986bf5..6c679e929 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -33,11 +33,6 @@ import sys Import('*') if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: - Source('2bit_local_pred.cc') - Source('btb.cc') - Source('ras.cc') - Source('tournament_pred.cc') - TraceFlag('CommitRate') TraceFlag('IEW') TraceFlag('IQ') @@ -69,7 +64,6 @@ if 'O3CPU' in env['CPU_MODELS']: Source('store_set.cc') Source('thread_context.cc') - TraceFlag('FreeList') TraceFlag('LSQ') TraceFlag('LSQUnit') TraceFlag('MemDepUnit') diff --git a/src/cpu/o3/ras.cc b/src/cpu/ras.cc index f9939259a..f9939259a 100644 --- a/src/cpu/o3/ras.cc +++ b/src/cpu/ras.cc diff --git a/src/cpu/o3/tournament_pred.cc b/src/cpu/tournament_pred.cc index ffb941c77..ffb941c77 100644 --- a/src/cpu/o3/tournament_pred.cc +++ b/src/cpu/tournament_pred.cc |