diff options
| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-07-06 18:45:15 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-07-06 18:45:15 -0700 |
| commit | 255f82a78320fed364cfa45bf0e65b341ab0bcb7 (patch) | |
| tree | d84e2290c795701003f164f650cdd738ab00dc14 /src | |
| parent | 4f833907812b50e8c6cce761d2f3c1f6fd07ae7b (diff) | |
| download | gem5-255f82a78320fed364cfa45bf0e65b341ab0bcb7.tar.xz | |
ruby: added generic dma machine
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/protocol/RubySlicc_Exports.sm | 1 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 2e4a16784..e8616521a 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -173,6 +173,7 @@ enumeration(GenericMachineType, desc="...", default="GenericMachineType_NULL") { L2Cache, desc="L2 Cache Mach"; L3Cache, desc="L3 Cache Mach"; Directory, desc="Directory Mach"; + DMA, desc="DMA Mach"; Collector, desc="Collector Mach"; L1Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)"; L2Cache_wCC, desc="L1 Cache Mach with Cache Coherence (used for miss latency profile)"; diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh index 1858085cc..2b7eb8b3b 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -151,6 +151,9 @@ ConvertMachToGenericMach(MachineType machType) if (machType == MachineType_Directory) return GenericMachineType_Directory; + if (machType == MACHINETYPE_DMA_ENUM) + return GenericMachineType_DMA; + panic("cannot convert to a GenericMachineType"); } |