scons: rename TraceFlags to DebugFlags

30 files changed, 185 insertions, 187 deletions

diff --git a/src/SConscript b/src/SConscript
index 46f770499..117f21394 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -270,7 +270,6 @@ def DebugFlag(name, desc=None):
     if name in debug_flags:
         raise AttributeError, "Flag %s already specified" % name
     debug_flags[name] = (name, (), desc)
-TraceFlag = DebugFlag
 
 def CompoundFlag(name, flags, desc=None):
     if name in debug_flags:
@@ -280,7 +279,6 @@ def CompoundFlag(name, flags, desc=None):
     debug_flags[name] = (name, compound, desc)
 
 Export('DebugFlag')
-Export('TraceFlag')
 Export('CompoundFlag')
 
 ########################################################################
diff --git a/src/arch/SConscript b/src/arch/SConscript
index 34367b274..a8b7f5354 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -126,7 +126,7 @@ isa_desc_builder = Builder(action=isa_desc_action, emitter=isa_desc_emitter)
 
 env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
 
-TraceFlag('IntRegs')
-TraceFlag('FloatRegs')
-TraceFlag('MiscRegs')
+DebugFlag('IntRegs')
+DebugFlag('FloatRegs')
+DebugFlag('MiscRegs')
 CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'MiscRegs' ])
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 51aff52f3..a907e52fb 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -65,10 +65,10 @@ if env['TARGET_ISA'] == 'arm':
     SimObject('ArmNativeTrace.py')
     SimObject('ArmTLB.py')
 
-    TraceFlag('Arm')
-    TraceFlag('TLBVerbose')
-    TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
-    TraceFlag('Predecoder', "Instructions returned by the predecoder")
+    DebugFlag('Arm')
+    DebugFlag('TLBVerbose')
+    DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
+    DebugFlag('Predecoder', "Instructions returned by the predecoder")
     if env['FULL_SYSTEM']:
         Source('interrupts.cc')
         Source('stacktrace.cc')
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 9e0275de7..46c0dd914 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -41,7 +41,7 @@ if env['TARGET_ISA'] == 'mips':
     Source('dsp.cc')
 
     SimObject('MipsTLB.py')
-    TraceFlag('MipsPRA')
+    DebugFlag('MipsPRA')
 
     if env['FULL_SYSTEM']:
         SimObject('MipsSystem.py')
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index 0f264d223..f96f12757 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -45,7 +45,7 @@ if env['TARGET_ISA'] == 'power':
     Source('utility.cc')
 
     SimObject('PowerTLB.py')
-    TraceFlag('Power')
+    DebugFlag('Power')
 
     if not env['FULL_SYSTEM']:
         Source('process.cc')
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index a8babc28f..cc13d56af 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -44,8 +44,8 @@ if env['TARGET_ISA'] == 'sparc':
     SimObject('SparcNativeTrace.py')
 
     SimObject('SparcTLB.py')
-    TraceFlag('Sparc', "Generic SPARC ISA stuff")
-    TraceFlag('RegisterWindows', "Register window manipulation")
+    DebugFlag('Sparc', "Generic SPARC ISA stuff")
+    DebugFlag('RegisterWindows', "Register window manipulation")
 
     if env['FULL_SYSTEM']:
         SimObject('SparcSystem.py')
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 9cb774647..2742c79e8 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -66,14 +66,14 @@ if env['TARGET_ISA'] == 'x86':
     SimObject('X86NativeTrace.py')
 
     SimObject('X86TLB.py')
-    TraceFlag('Predecoder', "Predecoder debug output")
-    TraceFlag('X86', "Generic X86 ISA debugging")
+    DebugFlag('Predecoder', "Predecoder debug output")
+    DebugFlag('X86', "Generic X86 ISA debugging")
 
     if env['FULL_SYSTEM']:
-        TraceFlag('LocalApic', "Local APIC debugging")
-        TraceFlag('PageTableWalker', \
+        DebugFlag('LocalApic', "Local APIC debugging")
+        DebugFlag('PageTableWalker', \
                   "Page table walker state machine debugging")
-        TraceFlag('Faults', "Trace all faults/exceptions/traps")
+        DebugFlag('Faults', "Trace all faults/exceptions/traps")
 
         SimObject('X86LocalApic.py')
         SimObject('X86System.py')
diff --git a/src/base/SConscript b/src/base/SConscript
index b6112e8c0..7c3b0786b 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -73,18 +73,18 @@ Source('loader/symtab.cc')
 
 Source('stats/text.cc')
 
-TraceFlag('Annotate', "State machine annotation debugging")
-TraceFlag('AnnotateQ', "State machine annotation queue debugging")
-TraceFlag('AnnotateVerbose', "Dump all state machine annotation details")
-TraceFlag('GDBAcc', "Remote debugger accesses")
-TraceFlag('GDBExtra', "Dump extra information on reads and writes")
-TraceFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.")
-TraceFlag('GDBRead', "Reads to the remote address space")
-TraceFlag('GDBRecv', "Messages received from the remote application")
-TraceFlag('GDBSend', "Messages sent to the remote application")
-TraceFlag('GDBWrite', "Writes to the remote address space")
-TraceFlag('SQL', "SQL queries sent to the server")
-TraceFlag('StatEvents', "Statistics event tracking")
+DebugFlag('Annotate', "State machine annotation debugging")
+DebugFlag('AnnotateQ', "State machine annotation queue debugging")
+DebugFlag('AnnotateVerbose', "Dump all state machine annotation details")
+DebugFlag('GDBAcc', "Remote debugger accesses")
+DebugFlag('GDBExtra', "Dump extra information on reads and writes")
+DebugFlag('GDBMisc', "Breakpoints, traps, watchpoints, etc.")
+DebugFlag('GDBRead', "Reads to the remote address space")
+DebugFlag('GDBRecv', "Messages received from the remote application")
+DebugFlag('GDBSend', "Messages sent to the remote application")
+DebugFlag('GDBWrite', "Writes to the remote address space")
+DebugFlag('SQL', "SQL queries sent to the server")
+DebugFlag('StatEvents', "Statistics event tracking")
 
 CompoundFlag('GDBAll',
     [ 'GDBMisc', 'GDBAcc', 'GDBRead', 'GDBWrite', 'GDBSend', 'GDBRecv',
diff --git a/src/base/vnc/SConscript b/src/base/vnc/SConscript
index c92676555..089509b9b 100644
--- a/src/base/vnc/SConscript
+++ b/src/base/vnc/SConscript
@@ -42,7 +42,7 @@ Import('*')
 if env['FULL_SYSTEM']:
     SimObject('VncServer.py')
     Source('vncserver.cc')
-    TraceFlag('VNC')
+    DebugFlag('VNC')
 
 Source('convert.cc')
 
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index f6ed80680..edb4b2702 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -137,7 +137,7 @@ if env['FULL_SYSTEM']:
 
 if env['USE_CHECKER']:
     Source('checker/cpu.cc')
-    TraceFlag('Checker')
+    DebugFlag('Checker')
     checker_supports = False
     for i in CheckerSupportedCPUList:
         if i in env['CPU_MODELS']:
@@ -149,32 +149,32 @@ if env['USE_CHECKER']:
         print ", please set USE_CHECKER=False or use one of those CPU models"
         Exit(1)
 
-TraceFlag('Activity')
-TraceFlag('Commit')
-TraceFlag('Context')
-TraceFlag('Decode')
-TraceFlag('DynInst')
-TraceFlag('ExecEnable')
-TraceFlag('ExecCPSeq')
-TraceFlag('ExecEffAddr')
-TraceFlag('ExecFaulting', 'Trace faulting instructions')
-TraceFlag('ExecFetchSeq')
-TraceFlag('ExecOpClass')
-TraceFlag('ExecRegDelta')
-TraceFlag('ExecResult')
-TraceFlag('ExecSpeculative')
-TraceFlag('ExecSymbol')
-TraceFlag('ExecThread')
-TraceFlag('ExecTicks')
-TraceFlag('ExecMicro')
-TraceFlag('ExecMacro')
-TraceFlag('ExecUser')
-TraceFlag('ExecKernel')
-TraceFlag('ExecAsid')
-TraceFlag('Fetch')
-TraceFlag('IntrControl')
-TraceFlag('PCEvent')
-TraceFlag('Quiesce')
+DebugFlag('Activity')
+DebugFlag('Commit')
+DebugFlag('Context')
+DebugFlag('Decode')
+DebugFlag('DynInst')
+DebugFlag('ExecEnable')
+DebugFlag('ExecCPSeq')
+DebugFlag('ExecEffAddr')
+DebugFlag('ExecFaulting', 'Trace faulting instructions')
+DebugFlag('ExecFetchSeq')
+DebugFlag('ExecOpClass')
+DebugFlag('ExecRegDelta')
+DebugFlag('ExecResult')
+DebugFlag('ExecSpeculative')
+DebugFlag('ExecSymbol')
+DebugFlag('ExecThread')
+DebugFlag('ExecTicks')
+DebugFlag('ExecMicro')
+DebugFlag('ExecMacro')
+DebugFlag('ExecUser')
+DebugFlag('ExecKernel')
+DebugFlag('ExecAsid')
+DebugFlag('Fetch')
+DebugFlag('IntrControl')
+DebugFlag('PCEvent')
+DebugFlag('Quiesce')
 
 CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
     'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
index b9c526763..aa579a179 100644
--- a/src/cpu/inorder/SConscript
+++ b/src/cpu/inorder/SConscript
@@ -34,28 +34,28 @@ if 'InOrderCPU' in env['CPU_MODELS']:
         SimObject('InOrderCPU.py')
         SimObject('InOrderTrace.py')
 
-        TraceFlag('ResReqCount')
-        TraceFlag('InOrderStage')
-        TraceFlag('InOrderStall')
-        TraceFlag('InOrderCPU')
-        TraceFlag('RegDepMap')
-        TraceFlag('InOrderDynInst')
-        TraceFlag('Resource')
-        TraceFlag('InOrderAGEN')
-        TraceFlag('InOrderFetchSeq')
-        TraceFlag('InOrderTLB')
-        TraceFlag('InOrderCachePort')
-        TraceFlag('InOrderBPred')
-        TraceFlag('InOrderDecode')
-        TraceFlag('InOrderExecute')
-        TraceFlag('InOrderInstBuffer')
-        TraceFlag('InOrderUseDef')
-        TraceFlag('InOrderMDU')
-        TraceFlag('InOrderGraduation')
-        TraceFlag('ThreadModel')
-        TraceFlag('RefCount')
-        TraceFlag('AddrDep')
-	TraceFlag('SkedCache')
+        DebugFlag('ResReqCount')
+        DebugFlag('InOrderStage')
+        DebugFlag('InOrderStall')
+        DebugFlag('InOrderCPU')
+        DebugFlag('RegDepMap')
+        DebugFlag('InOrderDynInst')
+        DebugFlag('Resource')
+        DebugFlag('InOrderAGEN')
+        DebugFlag('InOrderFetchSeq')
+        DebugFlag('InOrderTLB')
+        DebugFlag('InOrderCachePort')
+        DebugFlag('InOrderBPred')
+        DebugFlag('InOrderDecode')
+        DebugFlag('InOrderExecute')
+        DebugFlag('InOrderInstBuffer')
+        DebugFlag('InOrderUseDef')
+        DebugFlag('InOrderMDU')
+        DebugFlag('InOrderGraduation')
+        DebugFlag('ThreadModel')
+        DebugFlag('RefCount')
+        DebugFlag('AddrDep')
+        DebugFlag('SkedCache')
 
         CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
                'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 6c679e929..8ed337c25 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -33,9 +33,9 @@ import sys
 Import('*')
 
 if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
-    TraceFlag('CommitRate')
-    TraceFlag('IEW')
-    TraceFlag('IQ')
+    DebugFlag('CommitRate')
+    DebugFlag('IEW')
+    DebugFlag('IQ')
 
 if 'O3CPU' in env['CPU_MODELS']:
     SimObject('FUPool.py')
@@ -64,15 +64,15 @@ if 'O3CPU' in env['CPU_MODELS']:
     Source('store_set.cc')
     Source('thread_context.cc')
 
-    TraceFlag('LSQ')
-    TraceFlag('LSQUnit')
-    TraceFlag('MemDepUnit')
-    TraceFlag('O3CPU')
-    TraceFlag('ROB')
-    TraceFlag('Rename')
-    TraceFlag('Scoreboard')
-    TraceFlag('StoreSet')
-    TraceFlag('Writeback')
+    DebugFlag('LSQ')
+    DebugFlag('LSQUnit')
+    DebugFlag('MemDepUnit')
+    DebugFlag('O3CPU')
+    DebugFlag('ROB')
+    DebugFlag('Rename')
+    DebugFlag('Scoreboard')
+    DebugFlag('StoreSet')
+    DebugFlag('Writeback')
 
     CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
         'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
index 0ca1a0d07..d26410ac2 100644
--- a/src/cpu/ozone/SConscript
+++ b/src/cpu/ozone/SConscript
@@ -45,11 +45,11 @@ if 'OzoneCPU' in env['CPU_MODELS']:
     Source('lw_lsq.cc')
     Source('rename_table.cc')
 
-    TraceFlag('BE')
-    TraceFlag('FE')
-    TraceFlag('IBE')
-    TraceFlag('OzoneCPU')
-    TraceFlag('OzoneLSQ')
+    DebugFlag('BE')
+    DebugFlag('FE')
+    DebugFlag('IBE')
+    DebugFlag('OzoneCPU')
+    DebugFlag('OzoneLSQ')
 
     CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])
 
diff --git a/src/cpu/pred/SConscript b/src/cpu/pred/SConscript
index ce1dab9e2..742c132c7 100644
--- a/src/cpu/pred/SConscript
+++ b/src/cpu/pred/SConscript
@@ -35,4 +35,4 @@ if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
     Source('btb.cc')
     Source('ras.cc')
     Source('tournament.cc')
-    TraceFlag('FreeList')
+    DebugFlag('FreeList')
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index 76598666f..3b6b19c51 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -43,7 +43,7 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']:
 
 if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
        'TimingSimpleCPU' in env['CPU_MODELS']:
-    TraceFlag('SimpleCPU')
+    DebugFlag('SimpleCPU')
 
 if need_simple_base:
     Source('base.cc')
diff --git a/src/cpu/testers/directedtest/SConscript b/src/cpu/testers/directedtest/SConscript
index 1afa15984..a321a404c 100644
--- a/src/cpu/testers/directedtest/SConscript
+++ b/src/cpu/testers/directedtest/SConscript
@@ -45,4 +45,4 @@ Source('DirectedGenerator.cc')
 Source('SeriesRequestGenerator.cc')
 Source('InvalidateGenerator.cc')
 
-TraceFlag('DirectedTest')
+DebugFlag('DirectedTest')
diff --git a/src/cpu/testers/memtest/SConscript b/src/cpu/testers/memtest/SConscript
index 61aa0969e..566c4f2e4 100644
--- a/src/cpu/testers/memtest/SConscript
+++ b/src/cpu/testers/memtest/SConscript
@@ -35,4 +35,4 @@ SimObject('MemTest.py')
 
 Source('memtest.cc')
 
-TraceFlag('MemTest')
+DebugFlag('MemTest')
diff --git a/src/cpu/testers/networktest/SConscript b/src/cpu/testers/networktest/SConscript
index b658ac079..5b6b18d42 100644
--- a/src/cpu/testers/networktest/SConscript
+++ b/src/cpu/testers/networktest/SConscript
@@ -34,4 +34,4 @@ SimObject('NetworkTest.py')
 
 Source('networktest.cc', Werror=False)
 
-TraceFlag('NetworkTest')
+DebugFlag('NetworkTest')
diff --git a/src/cpu/testers/rubytest/SConscript b/src/cpu/testers/rubytest/SConscript
index 9352dd793..1b65932e7 100644
--- a/src/cpu/testers/rubytest/SConscript
+++ b/src/cpu/testers/rubytest/SConscript
@@ -44,4 +44,4 @@ Source('RubyTester.cc')
 Source('Check.cc')
 Source('CheckTable.cc')
 
-TraceFlag('RubyTest')
+DebugFlag('RubyTest')
diff --git a/src/dev/SConscript b/src/dev/SConscript
index 5243da683..744e7b3c1 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -76,31 +76,31 @@ if env['FULL_SYSTEM']:
     Source('uart.cc')
     Source('uart8250.cc')
 
-    TraceFlag('DiskImageRead')
-    TraceFlag('DiskImageWrite')
-    TraceFlag('DMA')
-    TraceFlag('DMACopyEngine')
-    TraceFlag('Ethernet')
-    TraceFlag('EthernetCksum')
-    TraceFlag('EthernetDMA')
-    TraceFlag('EthernetData')
-    TraceFlag('EthernetDesc')
-    TraceFlag('EthernetEEPROM')
-    TraceFlag('EthernetIntr')
-    TraceFlag('EthernetPIO')
-    TraceFlag('EthernetSM')
-    TraceFlag('IdeCtrl')
-    TraceFlag('IdeDisk')
-    TraceFlag('Intel8254Timer')
-    TraceFlag('IsaFake')
-    TraceFlag('MC146818')
-    TraceFlag('PCIDEV')
-    TraceFlag('PciConfigAll')
-    TraceFlag('SimpleDisk')
-    TraceFlag('SimpleDiskData')
-    TraceFlag('Terminal')
-    TraceFlag('TerminalVerbose')
-    TraceFlag('Uart')
+    DebugFlag('DiskImageRead')
+    DebugFlag('DiskImageWrite')
+    DebugFlag('DMA')
+    DebugFlag('DMACopyEngine')
+    DebugFlag('Ethernet')
+    DebugFlag('EthernetCksum')
+    DebugFlag('EthernetDMA')
+    DebugFlag('EthernetData')
+    DebugFlag('EthernetDesc')
+    DebugFlag('EthernetEEPROM')
+    DebugFlag('EthernetIntr')
+    DebugFlag('EthernetPIO')
+    DebugFlag('EthernetSM')
+    DebugFlag('IdeCtrl')
+    DebugFlag('IdeDisk')
+    DebugFlag('Intel8254Timer')
+    DebugFlag('IsaFake')
+    DebugFlag('MC146818')
+    DebugFlag('PCIDEV')
+    DebugFlag('PciConfigAll')
+    DebugFlag('SimpleDisk')
+    DebugFlag('SimpleDiskData')
+    DebugFlag('Terminal')
+    DebugFlag('TerminalVerbose')
+    DebugFlag('Uart')
 
     CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
     CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
diff --git a/src/dev/alpha/SConscript b/src/dev/alpha/SConscript
index 4dbb73903..32baa6f48 100644
--- a/src/dev/alpha/SConscript
+++ b/src/dev/alpha/SConscript
@@ -41,5 +41,5 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
     Source('tsunami_io.cc')
     Source('tsunami_pchip.cc')
 
-    TraceFlag('AlphaBackdoor')
-    TraceFlag('Tsunami')
+    DebugFlag('AlphaBackdoor')
+    DebugFlag('Tsunami')
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index df4b7f22c..a320d9f8e 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -53,7 +53,7 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
     Source('rv_ctrl.cc')
     Source('realview.cc')
 
-    TraceFlag('AMBA')
-    TraceFlag('PL111')
-    TraceFlag('Pl050')
-    TraceFlag('GIC')
+    DebugFlag('AMBA')
+    DebugFlag('PL111')
+    DebugFlag('Pl050')
+    DebugFlag('GIC')
diff --git a/src/dev/mips/SConscript b/src/dev/mips/SConscript
index ebb47da33..369dbfed2 100755
--- a/src/dev/mips/SConscript
+++ b/src/dev/mips/SConscript
@@ -34,7 +34,7 @@ Import('*')
 if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
     SimObject('Malta.py')
 
-    TraceFlag('Malta')
+    DebugFlag('Malta')
 
     Source('malta.cc')
     Source('malta_cchip.cc')
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
index b546297d1..772aa4864 100644
--- a/src/dev/sparc/SConscript
+++ b/src/dev/sparc/SConscript
@@ -39,4 +39,4 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
     Source('t1000.cc')
     Source('mm_disk.cc')
 
-    TraceFlag('Iob')
+    DebugFlag('Iob')
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 37b292f00..eeb68cf44 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -39,32 +39,32 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
 
     SimObject('Cmos.py')
     Source('cmos.cc')
-    TraceFlag('CMOS', 'Accesses to CMOS devices')
+    DebugFlag('CMOS', 'Accesses to CMOS devices')
 
     SimObject('I8259.py')
     Source('i8259.cc')
-    TraceFlag('I8259', 'Accesses to the I8259 PIC devices')
+    DebugFlag('I8259', 'Accesses to the I8259 PIC devices')
 
     SimObject('I8254.py')
     Source('i8254.cc')
-    TraceFlag('I8254', 'Interrupts from the I8254 timer');
+    DebugFlag('I8254', 'Interrupts from the I8254 timer');
 
     SimObject('I8237.py')
     Source('i8237.cc')
-    TraceFlag('I8237', 'The I8237 dma controller');
+    DebugFlag('I8237', 'The I8237 dma controller');
 
     SimObject('I8042.py')
     Source('i8042.cc')
-    TraceFlag('I8042', 'The I8042 keyboard controller');
+    DebugFlag('I8042', 'The I8042 keyboard controller');
 
     SimObject('PcSpeaker.py')
     Source('speaker.cc')
-    TraceFlag('PcSpeaker')
+    DebugFlag('PcSpeaker')
 
     SimObject('I82094AA.py')
     Source('i82094aa.cc')
-    TraceFlag('I82094AA')
+    DebugFlag('I82094AA')
 
     SimObject('X86IntPin.py')
     Source('intdev.cc')
-    TraceFlag('IntDev')
+    DebugFlag('IntDev')
diff --git a/src/kern/SConscript b/src/kern/SConscript
index 145f0d986..93394829b 100644
--- a/src/kern/SConscript
+++ b/src/kern/SConscript
@@ -37,8 +37,8 @@ if env['FULL_SYSTEM']:
     Source('kernel_stats.cc')
     Source('system_events.cc')
 
-    TraceFlag('DebugPrintf')
-    TraceFlag('Printf')
+    DebugFlag('DebugPrintf')
+    DebugFlag('Printf')
 
     Source('linux/events.cc')
     Source('linux/linux_syscalls.cc')
@@ -49,7 +49,7 @@ if env['FULL_SYSTEM']:
         Source('tru64/printf.cc')
         Source('tru64/tru64_events.cc')
         Source('tru64/tru64_syscalls.cc')
-        TraceFlag('BADADDR')
+        DebugFlag('BADADDR')
 else:
     Source('linux/linux.cc')
     Source('operatingsystem.cc')
diff --git a/src/mem/SConscript b/src/mem/SConscript
index a8c42df5a..298e1e09f 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -53,24 +53,24 @@ elif env['TARGET_ISA'] != 'no':
     Source('page_table.cc')
     Source('translating_port.cc')
 
-TraceFlag('Bus')
-TraceFlag('BusAddrRanges')
-TraceFlag('BusBridge')
-TraceFlag('LLSC')
-TraceFlag('MMU')
-TraceFlag('MemoryAccess')
+DebugFlag('Bus')
+DebugFlag('BusAddrRanges')
+DebugFlag('BusBridge')
+DebugFlag('LLSC')
+DebugFlag('MMU')
+DebugFlag('MemoryAccess')
 
-TraceFlag('ProtocolTrace')
-TraceFlag('RubyCache')
-TraceFlag('RubyDma')
-TraceFlag('RubyGenerated')
-TraceFlag('RubyMemory')
-TraceFlag('RubyNetwork')
-TraceFlag('RubyPort')
-TraceFlag('RubyQueue')
-TraceFlag('RubySlicc')
-TraceFlag('RubyStorebuffer')
-TraceFlag('RubyTester')
+DebugFlag('ProtocolTrace')
+DebugFlag('RubyCache')
+DebugFlag('RubyDma')
+DebugFlag('RubyGenerated')
+DebugFlag('RubyMemory')
+DebugFlag('RubyNetwork')
+DebugFlag('RubyPort')
+DebugFlag('RubyQueue')
+DebugFlag('RubySlicc')
+DebugFlag('RubyStorebuffer')
+DebugFlag('RubyTester')
 
 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
     'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', 
diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index 781521d3f..dc2270b08 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -42,7 +42,7 @@ Source('builder.cc')
 Source('mshr.cc')
 Source('mshr_queue.cc')
 
-TraceFlag('Cache')
-TraceFlag('CachePort')
-TraceFlag('CacheRepl')
-TraceFlag('HWPrefetch')
+DebugFlag('Cache')
+DebugFlag('CachePort')
+DebugFlag('CacheRepl')
+DebugFlag('HWPrefetch')
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index d640a9f13..a233e9684 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -42,5 +42,5 @@ Source('cacheset.cc')
 SimObject('iic_repl/Repl.py')
 Source('iic_repl/gen.cc')
 
-TraceFlag('IIC')
-TraceFlag('IICMore')
+DebugFlag('IIC')
+DebugFlag('IICMore')
diff --git a/src/sim/SConscript b/src/sim/SConscript
index b3065374b..041c3ac10 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -62,20 +62,20 @@ elif env['TARGET_ISA'] != 'no':
     Source('process.cc')
     Source('syscall_emul.cc')
 
-TraceFlag('Checkpoint')
-TraceFlag('Config')
-TraceFlag('Event')
-TraceFlag('Fault')
-TraceFlag('Flow')
-TraceFlag('IPI')
-TraceFlag('IPR')
-TraceFlag('Interrupt')
-TraceFlag('Loader')
-TraceFlag('Stack')
-TraceFlag('SyscallVerbose')
-TraceFlag('TimeSync')
-TraceFlag('TLB')
-TraceFlag('Thread')
-TraceFlag('Timer')
-TraceFlag('VtoPhys')
-TraceFlag('WorkItems')
+DebugFlag('Checkpoint')
+DebugFlag('Config')
+DebugFlag('Event')
+DebugFlag('Fault')
+DebugFlag('Flow')
+DebugFlag('IPI')
+DebugFlag('IPR')
+DebugFlag('Interrupt')
+DebugFlag('Loader')
+DebugFlag('Stack')
+DebugFlag('SyscallVerbose')
+DebugFlag('TimeSync')
+DebugFlag('TLB')
+DebugFlag('Thread')
+DebugFlag('Timer')
+DebugFlag('VtoPhys')
+DebugFlag('WorkItems')