Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 0c696374b19b27c0bd50ffa7f75117b1e211e4bc

8 files changed, 139 insertions, 225 deletions

diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 02f7cf61a..f9c750901 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -85,7 +85,12 @@ output header {{
             std::string generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const;
 
-            void printReg(std::ostream &os, int reg) const;
+            void printReg(std::ostream &os, RegIndex reg) const;
+            void printSrcReg(std::ostream &os, int reg) const;
+            void printDestReg(std::ostream &os, int reg) const;
+
+            void printRegArray(std::ostream &os,
+                const RegIndex indexArray[], int num) const;
         };
 
         bool passesCondition(uint32_t codes, uint32_t condition);
@@ -150,8 +155,35 @@ output decoder {{
             ccprintf(os, "\t%s   ", mnemonic);
         }
 
+        void SparcStaticInst::printRegArray(std::ostream &os,
+            const RegIndex indexArray[], int num) const
+        {
+            if(num <= 0)
+                return;
+            printReg(os, indexArray[0]);
+            for(int x = 1; x < num; x++)
+            {
+                os << ", ";
+                printReg(os, indexArray[x]);
+            }
+        }
+
+        void
+        SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
+        {
+            if(_numSrcRegs > reg)
+                printReg(os, _srcRegIdx[reg]);
+        }
+
+        void
+        SparcStaticInst::printDestReg(std::ostream &os, int reg) const
+        {
+            if(_numDestRegs > reg)
+                printReg(os, _destRegIdx[reg]);
+        }
+
         void
-        SparcStaticInst::printReg(std::ostream &os, int reg) const
+        SparcStaticInst::printReg(std::ostream &os, RegIndex reg) const
         {
             const int MaxGlobal = 8;
             const int MaxOutput = 16;
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index fa8832920..ca91f6755 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -39,30 +39,30 @@ decode OP default Unknown::unknown()
     {
         //Throw an illegal instruction acception
         0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
-        0x1: decode BPCC
+        format BranchN
         {
-            format Branch19
+            0x1: decode BPCC
             {
-                0x0: bpcci({{
+                0x0: bpcci(19, {{
                     if(passesCondition(Ccr<3:0>, COND2))
                         NNPC = xc->readPC() + disp;
                     else
                         handle_annul
                 }});
-                0x2: bpccx({{
+                0x2: bpccx(19, {{
                     if(passesCondition(Ccr<7:4>, COND2))
                         NNPC = xc->readPC() + disp;
                     else
                         handle_annul
                 }});
             }
+            0x2: bicc(22, {{
+                if(passesCondition(Ccr<3:0>, COND2))
+                    NNPC = xc->readPC() + disp;
+                else
+                    handle_annul
+            }});
         }
-        0x2: Branch22::bicc({{
-            if(passesCondition(Ccr<3:0>, COND2))
-                NNPC = xc->readPC() + disp;
-            else
-                handle_annul
-        }});
         0x3: decode RCOND2
         {
             format BranchSplit
@@ -110,7 +110,7 @@ decode OP default Unknown::unknown()
         0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
         0x6: Trap::fbfcc({{fault = new FpDisabled;}});
     }
-    0x1: Branch30::call({{
+    0x1: BranchN::call(30, {{
             R15 = xc->readPC();
             NNPC = R15 + disp;
     }});
@@ -325,12 +325,12 @@ decode OP default Unknown::unknown()
             0x28: rdasr({{
                 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
             }});
-            0x29: rdhpr({{
+            0x29: HPriv::rdhpr({{
                 // XXX Need to protect with format that traps non-priv/priv
                 // access
                 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
             }});
-            0x2A: rdpr({{
+            0x2A: Priv::rdpr({{
                 // XXX Need to protect with format that traps non-priv
                 // access
                 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
@@ -397,15 +397,15 @@ decode OP default Unknown::unknown()
                 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
                 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
             }
-            0x32: wrpr({{
+            0x32: Priv::wrpr({{
                 // XXX Need to protect with format that traps non-priv
                 // access
-                xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
+                fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
             }});
-            0x33: wrhpr({{
+            0x33: HPriv::wrhpr({{
                 // XXX Need to protect with format that traps non-priv/priv
                 // access
-                xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
+                fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
             }});
             0x34: Trap::fpop1({{fault = new FpDisabled;}});
             0x35: Trap::fpop2({{fault = new FpDisabled;}});
@@ -549,7 +549,7 @@ decode OP default Unknown::unknown()
                     NNPC = Tnpc + 4;
                     Tl = Tl - 1;
                 }});
-                0x1: BasicOperate::retry({{
+                0x1: Priv::retry({{
                     if(Tl == 0)
                         return new IllegalInstruction;
                     Cwp = Tstate<4:0>;
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 60432cb6b..0a47a7ffe 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -63,7 +63,6 @@ def template BasicExecute {{
         {
             Fault fault = NoFault;
 
-            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(code)s;
@@ -81,11 +80,6 @@ def template BasicDecode {{
         return new %(class_name)s(machInst);
 }};
 
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
-        return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
 // The most basic instruction format... used only for a few misc. insts
 def format BasicOperate(code, *flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst',
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index 7d46ce739..8a3f05173 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -69,47 +69,18 @@ output header {{
         };
 
         /**
-         * Base class for branches with 19 bit displacements.
+         * Base class for branches with n bit displacements.
          */
-        class Branch19 : public BranchDisp
+        template<int bits>
+        class BranchNBits : public BranchDisp
         {
           protected:
             // Constructor
-            Branch19(const char *mnem, MachInst _machInst,
+            BranchNBits(const char *mnem, MachInst _machInst,
                     OpClass __opClass) :
                 BranchDisp(mnem, _machInst, __opClass)
             {
-                disp = sign_ext(DISP19 << 2, 21);
-            }
-        };
-
-        /**
-         * Base class for branches with 22 bit displacements.
-         */
-        class Branch22 : public BranchDisp
-        {
-          protected:
-            // Constructor
-            Branch22(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                BranchDisp(mnem, _machInst, __opClass)
-            {
-                disp = sign_ext(DISP22 << 2, 24);
-            }
-        };
-
-        /**
-         * Base class for branches with 30 bit displacements.
-         */
-        class Branch30 : public BranchDisp
-        {
-          protected:
-            // Constructor
-            Branch30(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                BranchDisp(mnem, _machInst, __opClass)
-            {
-                disp = sign_ext(DISP30 << 2, 32);
+                disp = sign_ext(_machInst << 2, bits + 2);
             }
         };
 
@@ -149,29 +120,23 @@ output header {{
 }};
 
 output decoder {{
+
+        template class BranchNBits<19>;
+
+        template class BranchNBits<22>;
+
+        template class BranchNBits<30>;
+
         std::string Branch::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
 
             printMnemonic(response, mnemonic);
-
-            if (_numSrcRegs > 0)
-            {
-                printReg(response, _srcRegIdx[0]);
-                for(int x = 1; x < _numSrcRegs; x++)
-                {
+            printRegArray(response, _srcRegIdx, _numSrcRegs);
+            if(_numDestRegs && _numSrcRegs)
                     response << ", ";
-                    printReg(response, _srcRegIdx[x]);
-                }
-            }
-
-            if (_numDestRegs > 0)
-            {
-                if(_numSrcRegs > 0)
-                    response << ", ";
-                printReg(response, _destRegIdx[0]);
-            }
+            printDestReg(response, 0);
 
             return response.str();
         }
@@ -182,27 +147,13 @@ output decoder {{
             std::stringstream response;
 
             printMnemonic(response, mnemonic);
-
-            if (_numSrcRegs > 0)
-            {
-                printReg(response, _srcRegIdx[0]);
-                for(int x = 1; x < _numSrcRegs; x++)
-                {
-                    response << ", ";
-                    printReg(response, _srcRegIdx[x]);
-                }
-            }
-
+            printRegArray(response, _srcRegIdx, _numSrcRegs);
             if(_numSrcRegs > 0)
                 response << ", ";
-
             ccprintf(response, "0x%x", imm);
-
             if (_numDestRegs > 0)
-            {
                 response << ", ";
-                printReg(response, _destRegIdx[0]);
-            }
+            printDestReg(response, 0);
 
             return response.str();
         }
@@ -292,32 +243,10 @@ def format Branch(code, *opt_flags) {{
 }};
 
 // Primary format for branch instructions:
-def format Branch19(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch22(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch30(code, *opt_flags) {{
+def format BranchN(bits, code, *opt_flags) {{
         code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
+        iop = InstObjParams(name, Name, "BranchNBits<%d>" % bits, codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         exec_output = BranchExecute.subst(iop)
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 1894ce541..27616216e 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -132,7 +132,7 @@ output header {{
                     OpClass __opClass) :
                 IntOpImm(mnem, _machInst, __opClass)
             {
-                imm = (IMM22 << 10) & 0xFFFFFC00;
+                imm = (IMM22 & 0x3FFFFF) << 10;
             }
 
             std::string generateDisassembly(Addr pc,
@@ -157,12 +157,9 @@ output decoder {{
             if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
             {
                 printMnemonic(os, "mov");
-                if(_numSrcRegs > 0)
-                    printReg(os, _srcRegIdx[1]);
+                printSrcReg(os, 1);
                 ccprintf(os, ", ");
-                if(_numDestRegs > 0)
-                    printReg(os, _destRegIdx[0]);
-
+                printDestReg(os, 0);
                 return true;
             }
             return false;
@@ -173,32 +170,24 @@ output decoder {{
         {
             if(!strcmp(mnemonic, "or"))
             {
-                if(_srcRegIdx[0] == 0)
+                if(_numSrcRegs > 0 && _srcRegIdx[0] == 0)
                 {
                     if(imm == 0)
-                    {
                         printMnemonic(os, "clr");
-                        if(_numDestRegs > 0)
-                            printReg(os, _destRegIdx[0]);
-                        return true;
-                    }
                     else
                     {
                         printMnemonic(os, "mov");
-                        ccprintf(os, ", 0x%x, ", imm);
-                        if(_numDestRegs > 0)
-                            printReg(os, _destRegIdx[0]);
-                        return true;
+                        ccprintf(os, " 0x%x, ", imm);
                     }
+                    printDestReg(os, 0);
+                    return true;
                 }
                 else if(imm == 0)
                 {
                     printMnemonic(os, "mov");
-                    if(_numSrcRegs > 0)
-                        printReg(os, _srcRegIdx[0]);
+                    printSrcReg(os, 0);
                     ccprintf(os, ", ");
-                    if(_numDestRegs > 0)
-                        printReg(os, _destRegIdx[0]);
+                    printDestReg(os, 0);
                     return true;
                 }
             }
@@ -210,25 +199,13 @@ output decoder {{
         {
             std::stringstream response;
 
-            if(!printPseudoOps(response, pc, symtab))
-            {
-                printMnemonic(response, mnemonic);
-                if (_numSrcRegs > 0)
-                {
-                    printReg(response, _srcRegIdx[0]);
-                    for(int x = 1; x < _numSrcRegs; x++)
-                    {
-                        response << ", ";
-                        printReg(response, _srcRegIdx[x]);
-                    }
-                }
-                if (_numDestRegs > 0)
-                {
-                    if(_numSrcRegs > 0)
-                        response << ", ";
-                    printReg(response, _destRegIdx[0]);
-                }
-            }
+            if(printPseudoOps(response, pc, symtab))
+                return response.str();
+            printMnemonic(response, mnemonic);
+            printRegArray(response, _srcRegIdx, _numSrcRegs);
+            if(_numDestRegs && _numSrcRegs)
+                response << ", ";
+            printDestReg(response, 0);
             return response.str();
         }
 
@@ -237,27 +214,16 @@ output decoder {{
         {
             std::stringstream response;
 
-            if(!printPseudoOps(response, pc, symtab))
-            {
-                printMnemonic(response, mnemonic);
-                if (_numSrcRegs > 0)
-                {
-                    printReg(response, _srcRegIdx[0]);
-                    for(int x = 1; x < _numSrcRegs - 1; x++)
-                    {
-                        response << ", ";
-                        printReg(response, _srcRegIdx[x]);
-                    }
-                }
-                if(_numSrcRegs > 0)
-                    response << ", ";
-                ccprintf(response, "0x%x", imm);
-                if (_numDestRegs > 0)
-                {
-                    response << ", ";
-                    printReg(response, _destRegIdx[0]);
-                }
-            }
+            if(printPseudoOps(response, pc, symtab))
+                return response.str();
+            printMnemonic(response, mnemonic);
+            printRegArray(response, _srcRegIdx, _numSrcRegs);
+            if(_numSrcRegs > 0)
+                response << ", ";
+            ccprintf(response, "0x%x", imm);
+            if(_numDestRegs > 0)
+                response << ", ";
+            printDestReg(response, 0);
             return response.str();
         }
 
@@ -267,10 +233,8 @@ output decoder {{
             std::stringstream response;
 
             printMnemonic(response, mnemonic);
-            if(_numSrcRegs > 0)
-                response << ", ";
             ccprintf(response, "%%hi(0x%x), ", imm);
-            printReg(response, _destRegIdx[0]);
+            printDestReg(response, 0);
             return response.str();
         }
 }};
@@ -316,38 +280,29 @@ let {{
         return (header_output, decoder_output, exec_output, decode_block)
 
     calcCcCode = '''
-        uint8_t tmp_ccriccc;
-        uint8_t tmp_ccriccv;
-        uint8_t tmp_ccriccz;
-        uint8_t tmp_ccriccn;
-        uint8_t tmp_ccrxccc;
-        uint8_t tmp_ccrxccv;
-        uint8_t tmp_ccrxccz;
-        uint8_t tmp_ccrxccn;
-
-        tmp_ccriccn = (Rd >> 31) & 1;
-        tmp_ccriccz = ((Rd & 0xFFFFFFFF) == 0);
-        tmp_ccrxccn = (Rd >> 63) & 1;
-        tmp_ccrxccz = (Rd == 0);
-        tmp_ccriccv = %(ivValue)s & 1;
-        tmp_ccriccc = %(icValue)s & 1;
-        tmp_ccrxccv = %(xvValue)s & 1;
-        tmp_ccrxccc = %(xcValue)s & 1;
-
-        Ccr =  tmp_ccriccc | tmp_ccriccv << 1 |
-               tmp_ccriccz << 2 | tmp_ccriccn << 3|
-               tmp_ccrxccc << 4 | tmp_ccrxccv << 5|
-               tmp_ccrxccz << 6| tmp_ccrxccn << 7;
-
-
-        DPRINTF(Sparc, "in = %%d\\n", (uint16_t)tmp_ccriccn);
-        DPRINTF(Sparc, "iz = %%d\\n", (uint16_t)tmp_ccriccz);
-        DPRINTF(Sparc, "xn = %%d\\n", (uint16_t)tmp_ccrxccn);
-        DPRINTF(Sparc, "xz = %%d\\n", (uint16_t)tmp_ccrxccz);
-        DPRINTF(Sparc, "iv = %%d\\n", (uint16_t)tmp_ccriccv);
-        DPRINTF(Sparc, "ic = %%d\\n", (uint16_t)tmp_ccriccc);
-        DPRINTF(Sparc, "xv = %%d\\n", (uint16_t)tmp_ccrxccv);
-        DPRINTF(Sparc, "xc = %%d\\n", (uint16_t)tmp_ccrxccc);
+        uint16_t _ic, _iv, _iz, _in, _xc, _xv, _xz, _xn;
+
+        _in = (Rd >> 31) & 1;
+        _iz = ((Rd & 0xFFFFFFFF) == 0);
+        _xn = (Rd >> 63) & 1;
+        _xz = (Rd == 0);
+        _iv = %(ivValue)s & 1;
+        _ic = %(icValue)s & 1;
+        _xv = %(xvValue)s & 1;
+        _xc = %(xcValue)s & 1;
+
+        Ccr =  _ic << 0 | _iv << 1 | _iz << 2 | _in << 3 |
+               _xc << 4 | _xv << 5 | _xz << 6 | _xn << 7;
+
+
+        DPRINTF(Sparc, "in = %%d\\n", _in);
+        DPRINTF(Sparc, "iz = %%d\\n", _iz);
+        DPRINTF(Sparc, "xn = %%d\\n", _xn);
+        DPRINTF(Sparc, "xz = %%d\\n", _xz);
+        DPRINTF(Sparc, "iv = %%d\\n", _iv);
+        DPRINTF(Sparc, "ic = %%d\\n", _ic);
+        DPRINTF(Sparc, "xv = %%d\\n", _xv);
+        DPRINTF(Sparc, "xc = %%d\\n", _xc);
         '''
 }};
 
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 7df59d736..d7ee01519 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -72,7 +72,11 @@ output decoder {{
         std::string Priv::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
-                return "Privileged Instruction";
+            std::stringstream response;
+
+            printMnemonic(response, mnemonic);
+
+            return response.str();
         }
 }};
 
@@ -87,9 +91,10 @@ def template PrivExecute {{
         if(%(check)s)
             return new PrivilegedAction;
 
+        Fault fault = NoFault;
         %(code)s;
         %(op_wb)s;
-        return NoFault;
+        return fault;
     }
 }};
 
@@ -116,10 +121,17 @@ let {{
 
 // Primary format for integer operate instructions:
 def format Priv(code, *opt_flags) {{
-        checkCode = "((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>)"
+        checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
+                        ((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
         (header_output, decoder_output,
          exec_output, decode_block) = doPrivFormat(code,
-             checkCode, name, Name, opt_flags)
+             checkCode, name, Name, opt_flags + ('IprAccessOp',))
 }};
 
+def format HPriv(code, *opt_flags) {{
+        checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
+        (header_output, decoder_output,
+         exec_output, decode_block) = doPrivFormat(code,
+             checkCode, name, Name, opt_flags + ('IprAccessOp',))
+}};
 
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 40afb3722..3783051c4 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -36,7 +36,6 @@
 output header {{
 #include <sstream>
 #include <iostream>
-#include <iomanip>
 
 #include "cpu/static_inst.hh"
 #include "arch/sparc/faults.hh"
@@ -50,7 +49,6 @@ output decoder {{
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"  // for Jump::branchTarget()
 
-#include <math.h>
 #if defined(linux)
 #include <fenv.h>
 #endif
@@ -59,14 +57,10 @@ using namespace SparcISA;
 }};
 
 output exec {{
-#include <math.h>
 #if defined(linux)
 #include <fenv.h>
 #endif
 
-#ifdef FULL_SYSTEM
-//#include "sim/pseudo_inst.hh"
-#endif
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh
index cbeb3c7b9..e5192d684 100644
--- a/src/arch/sparc/regfile.hh
+++ b/src/arch/sparc/regfile.hh
@@ -55,14 +55,12 @@ namespace SparcISA
     // NWINDOWS - number of register windows, can be 3 to 32
     const int NWindows = 32;
 
-
     const int AsrStart = 0;
     const int PrStart = 32;
     const int HprStart = 64;
     const int MiscStart = 96;
 
     const uint64_t Bit64 = (1ULL << 63);
-
     class IntRegFile
     {
       protected:
@@ -625,11 +623,9 @@ namespace SparcISA
             hpstateFields.red = 1;
             hpstateFields.hpriv = 1;
             hpstateFields.tlz = 0; // this is a guess
-
             hintp = 0; // no interrupts pending
             hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
             hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
-
 #else
 /*	    //This sets up the initial state of the processor for usermode processes
             pstateFields.priv = 0; //Process runs in user mode
@@ -687,6 +683,8 @@ namespace SparcISA
 
         void copyMiscRegs(ThreadContext * tc);
 
+      protected:
+
         bool isHyperPriv() { return hpstateFields.hpriv; }
         bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
         bool isNonPriv() { return !isPriv(); }