cpu: add support for outputing a protobuf formatted CPU trace

Doesn't support x86 due to static instruction representation.

--HG--
rename : src/cpu/CPUTracers.py => src/cpu/InstPBTrace.py

6 files changed, 463 insertions, 0 deletions

diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py
new file mode 100644
index 000000000..2576fc944
--- /dev/null
+++ b/src/cpu/InstPBTrace.py
@@ -0,0 +1,37 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+from m5.params import *
+from InstTracer import InstTracer
+
+class InstPBTrace(InstTracer):
+    type = 'InstPBTrace'
+    cxx_class = 'Trace::InstPBTrace'
+    cxx_header = 'cpu/inst_pb_trace.hh'
+    file_name = Param.String("Instruction trace output file")
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 22388e6d9..f2c4f2c06 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -35,6 +35,11 @@ if env['TARGET_ISA'] == 'null':
     Source('intr_control_noisa.cc')
     Return()
 
+# Only build the protocol buffer instructions tracer if we have protobuf support
+if env['HAVE_PROTOBUF'] and env['TARGET_ISA'] != 'x86':
+    SimObject('InstPBTrace.py')
+    Source('inst_pb_trace.cc')
+
 SimObject('CheckerCPU.py')
 
 SimObject('BaseCPU.py')
diff --git a/src/cpu/inst_pb_trace.cc b/src/cpu/inst_pb_trace.cc
new file mode 100644
index 000000000..e6ed425ec
--- /dev/null
+++ b/src/cpu/inst_pb_trace.cc
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#include "cpu/inst_pb_trace.hh"
+
+#include "base/callback.hh"
+#include "base/output.hh"
+#include "config/the_isa.hh"
+#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "debug/ExecEnable.hh"
+#include "params/InstPBTrace.hh"
+#include "proto/inst.pb.h"
+#include "sim/core.hh"
+
+namespace Trace {
+
+ProtoOutputStream *InstPBTrace::traceStream;
+
+void
+InstPBTraceRecord::dump()
+{
+    // We're trying to build an instruction trace so we just want macro-ops and
+    // instructions that aren't macro-oped
+    if ((macroStaticInst && staticInst->isFirstMicroop()) ||
+            !staticInst->isMicroop()) {
+        tracer.traceInst(thread, staticInst, pc);
+    }
+
+    // If this instruction accessed memory lets record it
+    if (getMemValid())
+        tracer.traceMem(staticInst, getAddr(), getSize(), getFlags());
+}
+
+InstPBTrace::InstPBTrace(const InstPBTraceParams *p)
+    : InstTracer(p), curMsg(nullptr)
+{
+    // Create our output file
+    createTraceFile(p->file_name);
+}
+
+void
+InstPBTrace::createTraceFile(std::string filename)
+{
+    // Since there is only one output file for all tracers check if it exists
+    if (traceStream)
+        return;
+
+    traceStream = new ProtoOutputStream(simout.resolve(filename));
+
+    // Output the header
+    ProtoMessage::InstHeader header_msg;
+    header_msg.set_obj_id("gem5 generated instruction trace");
+    header_msg.set_ver(0);
+    header_msg.set_tick_freq(SimClock::Frequency);
+    header_msg.set_has_mem(true);
+    traceStream->write(header_msg);
+
+    // get a callback when we exit so we can close the file
+    Callback *cb = new MakeCallback<InstPBTrace,
+             &InstPBTrace::closeStreams>(this);
+    registerExitCallback(cb);
+}
+
+void
+InstPBTrace::closeStreams()
+{
+    if (curMsg) {
+        traceStream->write(*curMsg);
+        delete curMsg;
+        curMsg = NULL;
+    }
+
+    if (!traceStream)
+        return;
+
+    delete traceStream;
+    traceStream = NULL;
+}
+
+InstPBTrace::~InstPBTrace()
+{
+    closeStreams();
+}
+
+InstPBTraceRecord*
+InstPBTrace::getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr si,
+                           TheISA::PCState pc, const StaticInstPtr mi)
+{
+    // Only record the trace if Exec debugging in enabled
+    if (!Trace::enabled || !Debug::ExecEnable)
+        return NULL;
+
+    return new InstPBTraceRecord(*this, when, tc, si, pc, mi);
+
+}
+
+void
+InstPBTrace::traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc)
+{
+    if (curMsg) {
+        /// @todo if we are running multi-threaded I assume we'd need a lock here
+        traceStream->write(*curMsg);
+        delete curMsg;
+        curMsg = NULL;
+    }
+
+    // Create a new instruction message and fill out the fields
+    curMsg = new ProtoMessage::Inst;
+    curMsg->set_pc(pc.pc());
+    curMsg->set_inst(static_cast<uint32_t>(bits(si->machInst, 31, 0)));
+    curMsg->set_cpuid(tc->cpuId());
+    curMsg->set_tick(curTick());
+    curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
+    curMsg->set_inst_flags(bits(si->machInst, 7, 0));
+
+}
+
+void
+InstPBTrace::traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f)
+{
+    panic_if(!curMsg, "Memory access w/o msg?!");
+
+    // We do a poor job identifying macro-ops that are load/stores
+    curMsg->set_type(static_cast<ProtoMessage::Inst_InstType>(si->opClass()));
+
+    ProtoMessage::Inst::MemAccess *mem_msg = curMsg->add_mem_access();
+    mem_msg->set_addr(a);
+    mem_msg->set_size(s);
+    mem_msg->set_mem_flags(f);
+
+}
+
+} // namespace Trace
+
+
+Trace::InstPBTrace*
+InstPBTraceParams::create()
+{
+    return new Trace::InstPBTrace(this);
+}
+
diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
new file mode 100644
index 000000000..326f8b93a
--- /dev/null
+++ b/src/cpu/inst_pb_trace.hh
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2014 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __CPU_INST_PB_TRACE_HH__
+#define __CPU_INST_PB_TRACE_HH__
+
+#include "arch/types.hh"
+#include "base/trace.hh"
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
+#include "params/InstPBTrace.hh"
+#include "proto/protoio.hh"
+#include "sim/insttracer.hh"
+
+class ThreadContext;
+
+namespace ProtoMessage {
+class Inst;
+}
+
+namespace Trace {
+
+/**
+ * This in an instruction tracer that records the flow of instructions through
+ * multiple cpus and systems to a protobuf file specified by proto/inst.proto
+ * for further analysis.
+ */
+
+class InstPBTraceRecord : public InstRecord
+{
+  public:
+    InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc,
+                      const StaticInstPtr si, TheISA::PCState pc,
+                      const StaticInstPtr mi = NULL)
+        : InstRecord(when, tc, si, pc, mi), tracer(_tracer)
+    {}
+
+    /** called by the cpu when the instruction commits.
+     * This implementation of dump calls InstPBTrace to output the contents to a
+     * protobuf file
+     */
+    void dump() M5_ATTR_OVERRIDE;
+
+  protected:
+    InstPBTrace& tracer;
+
+};
+
+class InstPBTrace : InstTracer
+{
+ public:
+    InstPBTrace(const InstPBTraceParams *p);
+    virtual ~InstPBTrace();
+
+    InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
+                                    StaticInstPtr si, TheISA::PCState pc, const
+                                    StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE;
+
+  protected:
+    /** One output stream for the entire simulation.
+     * We encode the CPU & system ID so all we need is a single file
+     */
+    static ProtoOutputStream *traceStream;
+
+
+    /** This is the message were working on writing. The majority of the message
+     * exists however the memory accesses will be delayed.
+     */
+    ProtoMessage::Inst *curMsg;
+
+    /** Create the output file and write the header into it
+     * @param filename the file to create (if ends with .gz it will be
+     * compressed)
+     */
+    void createTraceFile(std::string filename);
+
+    /** If there is a pending message still write it out and then close the file
+     */
+    void closeStreams();
+
+    /** Write an instruction to the trace file
+     * @param tc thread context for the cpu ID
+     * @param si for the machInst and opClass
+     * @param pc for the PC Addr
+     */
+    void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
+
+    /** Write a memory request to the trace file as part of the cur instruction
+     * @param si for the machInst and opClass
+     * @param a address of the request
+     * @param s size of the request
+     * @param f flags for the request
+     */
+    void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f);
+
+    friend class InstPBTraceRecord;
+};
+} // namespace Trace
+#endif // __CPU_INST_PB_TRACE_HH__
diff --git a/src/proto/SConscript b/src/proto/SConscript
index 9bb6fd428..292a23639 100644
--- a/src/proto/SConscript
+++ b/src/proto/SConscript
@@ -42,4 +42,5 @@ Import('*')
 # Only build if we have protobuf support
 if env['HAVE_PROTOBUF']:
     ProtoBuf('packet.proto')
+    ProtoBuf('inst.proto')
     Source('protoio.cc')
diff --git a/src/proto/inst.proto b/src/proto/inst.proto
new file mode 100644
index 000000000..3e8dcde8b
--- /dev/null
+++ b/src/proto/inst.proto
@@ -0,0 +1,107 @@
+// Copyright (c) 2014 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Ali Saidi
+
+
+// Put all the generated messages in a namespace
+package ProtoMessage;
+
+// Packet header with the identifier describing what object captured
+// the trace, the version of this file format, and the tick frequency
+// for all the packet time stamps.
+message InstHeader {
+  required string obj_id = 1;
+  required uint32 ver = 2 [default = 0];
+  required uint64 tick_freq = 3;
+  required bool has_mem = 4;
+}
+
+message Inst {
+  required uint64 pc = 1;
+  required fixed32 inst = 2;
+  optional uint32 nodeid = 3;
+  optional uint32 cpuid = 4;
+  optional fixed64 tick = 5;
+
+  enum InstType {
+    None = 0;
+    IntAlu = 1;
+    IntMul = 2;
+    IntDiv = 3;
+    FloatAdd = 4;
+    FloatCmp = 5;
+    FloatCvt = 6;
+    FloatMult = 7;
+    FloatDiv = 8;
+    FloatSqrt = 9;
+    SIMDIntAdd = 10;
+    SIMDIntAddAcc = 11;
+    SIMDIntAlu = 12;
+    SIMDIntCmp = 13;
+    SIMDIntCvt = 14;
+    SIMDMisc = 15;
+    SIMDIntMult = 16;
+    SIMDIntMultAcc = 17;
+    SIMDIntShift = 18;
+    SIMDIntShiftAcc = 19;
+    SIMDSqrt = 20;
+    SIMDFloatAdd = 21;
+    SIMDFloatAlu = 22;
+    SIMDFloatCmp = 23;
+    SIMDFloatCvt = 24;
+    SIMDFloatDiv = 25;
+    SIMDFloatMisc = 26;
+    SIMDFloatMult = 27;
+    SIMDFloatMultAdd = 28;
+    SIMDFloatSqrt = 29;
+    MemRead = 30;
+    MemWrite = 31;
+    IprAccess = 32;
+    InstPrefetch = 33;
+  }
+
+  optional InstType type = 6; // add, mul, fp add, load, store, simd add, …
+  optional uint32 inst_flags = 7; // execution mode information
+
+  // If the operation does one or more memory accesses
+  message MemAccess {
+      required uint64 addr = 1;
+      required uint32 size = 2;
+      optional uint32 mem_flags = 3;
+  }
+  repeated MemAccess mem_access = 8;
+}
+