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authorLisa Hsu <hsul@eecs.umich.edu>2006-10-11 18:44:48 -0400
committerLisa Hsu <hsul@eecs.umich.edu>2006-10-11 18:44:48 -0400
commit024b33a1ef6f83be634f7afe644777f070ccd692 (patch)
tree87599f37a75a39070ed0e6a609aded7e1a655caf /src
parent727dea78c4b603a63d6c8bee10d317cb2905ffd4 (diff)
downloadgem5-024b33a1ef6f83be634f7afe644777f070ccd692.tar.xz
some drain changes in timing (kevin's) and some memory mode assertion changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc: memory mode assertion change so that it only goes off if it's supposed to. src/cpu/simple/timing.cc: some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to. --HG-- extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3
Diffstat (limited to 'src')
-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/timing.cc23
2 files changed, 14 insertions, 11 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 490be20ae..fe421ae6c 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -182,9 +182,9 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
void
AtomicSimpleCPU::resume()
{
- assert(system->getMemoryMode() == System::Atomic);
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
+ assert(system->getMemoryMode() == System::Atomic);
if (!tickEvent.scheduled())
tickEvent.schedule(curTick);
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 48362c42a..88aa882e3 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -146,6 +146,8 @@ void
TimingSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
+ assert(system->getMemoryMode() == System::Timing);
+
// Delete the old event if it existed.
if (fetchEvent) {
if (fetchEvent->scheduled())
@@ -159,7 +161,6 @@ TimingSimpleCPU::resume()
fetchEvent->schedule(curTick);
}
- assert(system->getMemoryMode() == System::Timing);
changeState(SimObject::Running);
}
@@ -190,6 +191,10 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
break;
}
}
+
+ if (_status != Running) {
+ _status = Idle;
+ }
}
@@ -533,15 +538,6 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
assert(_status == DcacheWaitResponse);
_status = Running;
- if (getState() == SimObject::Draining) {
- completeDrain();
-
- delete pkt->req;
- delete pkt;
-
- return;
- }
-
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
if (pkt->isRead() && pkt->req->isLocked()) {
@@ -551,6 +547,13 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
delete pkt->req;
delete pkt;
+ if (getState() == SimObject::Draining) {
+ advancePC(fault);
+ completeDrain();
+
+ return;
+ }
+
postExecute();
advanceInst(fault);
}