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authorGabe Black <gblack@eecs.umich.edu>2007-04-05 11:35:31 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-04-05 11:35:31 +0000
commit077183f7ece6aa7fcb009fb078e2e1a3370f9327 (patch)
tree3e9d50d4583a196f54b166ab1d92577f8f6cabaa /src
parent3d2a434e42b10ef30bbb590722e72ed104be669a (diff)
parentff7b89beeeabec340d5b84ed813466682a93f928 (diff)
downloadgem5-077183f7ece6aa7fcb009fb078e2e1a3370f9327.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : efdbf9787383dc1df544b7276f8120285e69bf69
Diffstat (limited to 'src')
-rwxr-xr-xsrc/arch/isa_parser.py8
-rw-r--r--src/arch/x86/intregs.hh84
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa22
-rw-r--r--src/arch/x86/isa/formats/multi.isa147
-rw-r--r--src/arch/x86/isa/main.isa3
-rw-r--r--src/arch/x86/isa/microasm.isa182
-rw-r--r--src/arch/x86/isa/microops/base.isa172
-rw-r--r--src/arch/x86/isa/microops/microops.isa5
-rw-r--r--src/arch/x86/isa/operands.isa6
-rw-r--r--src/arch/x86/types.hh21
-rw-r--r--src/arch/x86/utility.hh11
11 files changed, 482 insertions, 179 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index a0d671da1..4c8d0706d 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -866,7 +866,11 @@ class Format:
context = {}
updateExportContext()
context.update(exportContext)
- context.update({ 'name': name, 'Name': string.capitalize(name) })
+ if len(name):
+ Name = name[0].upper()
+ if len(name) > 1:
+ Name += name[1:]
+ context.update({ 'name': name, 'Name': Name })
try:
vars = self.func(self.user_code, context, *args[0], **args[1])
except Exception, exc:
@@ -1028,7 +1032,7 @@ def substBitOps(code):
# Template objects are format strings that allow substitution from
# the attribute spaces of other objects (e.g. InstObjParams instances).
-labelRE = re.compile(r'[^%]%\(([^\)]+)\)[sd]')
+labelRE = re.compile(r'(?<!%)%\(([^\)]+)\)[sd]')
class Template:
def __init__(self, t):
diff --git a/src/arch/x86/intregs.hh b/src/arch/x86/intregs.hh
index ed801cc48..562539de9 100644
--- a/src/arch/x86/intregs.hh
+++ b/src/arch/x86/intregs.hh
@@ -63,21 +63,89 @@ namespace X86ISA
enum IntRegIndex
{
INTREG_RAX,
+ INTREG_EAX = INTREG_RAX,
+ INTREG_AX = INTREG_RAX,
+ INTREG_AL = INTREG_RAX,
+ INTREG_AH = INTREG_RAX,
+
INTREG_RCX,
+ INTREG_ECX = INTREG_RCX,
+ INTREG_CX = INTREG_RCX,
+ INTREG_CL = INTREG_RCX,
+ INTREG_CH = INTREG_RCX,
+
INTREG_RDX,
+ INTREG_EDX = INTREG_RDX,
+ INTREG_DX = INTREG_RDX,
+ INTREG_DL = INTREG_RDX,
+ INTREG_DH = INTREG_RDX,
+
INTREG_RBX,
+ INTREG_EBX = INTREG_RBX,
+ INTREG_BX = INTREG_RBX,
+ INTREG_BL = INTREG_RBX,
+ INTREG_BH = INTREG_RBX,
+
INTREG_RSP,
+ INTREG_ESP = INTREG_RSP,
+ INTREG_SP = INTREG_RSP,
+ INTREG_SPL = INTREG_RSP,
+
INTREG_RBP,
+ INTREG_EBP = INTREG_RBP,
+ INTREG_BP = INTREG_RBP,
+ INTREG_BPL = INTREG_RBP,
+
INTREG_RSI,
+ INTREG_ESI = INTREG_RSI,
+ INTREG_SI = INTREG_RSI,
+ INTREG_SIL = INTREG_RSI,
+
INTREG_RDI,
- INTREG_R8W,
- INTREG_R9W,
- INTREG_R10W,
- INTREG_R11W,
- INTREG_R12W,
- INTREG_R13W,
- INTREG_R14W,
- INTREG_R15W,
+ INTREG_EDI = INTREG_RDI,
+ INTREG_DI = INTREG_RDI,
+ INTREG_DIL = INTREG_RDI,
+
+ INTREG_R8,
+ INTREG_R8D = INTREG_R8,
+ INTREG_R8W = INTREG_R8,
+ INTREG_R8B = INTREG_R8,
+
+ INTREG_R9,
+ INTREG_R9D = INTREG_R9,
+ INTREG_R9W = INTREG_R9,
+ INTREG_R9B = INTREG_R9,
+
+ INTREG_R10,
+ INTREG_R10D = INTREG_R10,
+ INTREG_R10W = INTREG_R10,
+ INTREG_R10B = INTREG_R10,
+
+ INTREG_R11,
+ INTREG_R11D = INTREG_R11,
+ INTREG_R11W = INTREG_R11,
+ INTREG_R11B = INTREG_R11,
+
+ INTREG_R12,
+ INTREG_R12D = INTREG_R12,
+ INTREG_R12W = INTREG_R12,
+ INTREG_R12B = INTREG_R12,
+
+ INTREG_R13,
+ INTREG_R13D = INTREG_R13,
+ INTREG_R13W = INTREG_R13,
+ INTREG_R13B = INTREG_R13,
+
+ INTREG_R14,
+ INTREG_R14D = INTREG_R14,
+ INTREG_R14W = INTREG_R14,
+ INTREG_R14B = INTREG_R14,
+
+ INTREG_R15,
+ INTREG_R15D = INTREG_R15,
+ INTREG_R15W = INTREG_R15,
+ INTREG_R15B = INTREG_R15,
+
NUM_INTREGS
};
};
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index f7e6e3994..fed6dda28 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -61,15 +61,12 @@
0x1: decode OPCODE_OP_TOP5 {
format WarnUnimpl {
0x00: decode OPCODE_OP_BOTTOM3 {
- 0x4: TaggedOp::add({{AddI %0 %0}}, [rAl]);
- 0x5: TaggedOp::add({{AddI %0 %0}}, [rAx]);
+ 0x4: Inst::add(rAl,Ib);
+ 0x5: Inst::add(rAx,Iz);
0x6: push_ES();
0x7: pop_ES();
- default: MultiOp::add(
- {{Add %0 %0 %1}},
- OPCODE_OP_BOTTOM3,
- [[Eb,Gb],[Ev,Gv],
- [Gb,Eb],[Gv,Ev]]);
+ default: MultiInst::add(OPCODE_OP_BOTTOM3,
+ [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]);
}
0x01: decode OPCODE_OP_BOTTOM3 {
0x0: or_Eb_Gb();
@@ -126,16 +123,13 @@
0x7: das();
}
0x06: decode OPCODE_OP_BOTTOM3 {
- 0x4: TaggedOp::xor({{XorI %0 %0}}, [rAl]);
- 0x5: TaggedOp::xor({{XorI %0 %0}}, [rAx]);
+ 0x4: Inst::xor(rAl,Ib);
+ 0x5: Inst::xor(rAx,Iz);
0x6: M5InternalError::error(
{{"Tried to execute the SS segment override prefix!"}});
0x7: aaa();
- default: MultiOp::xor(
- {{Xor %0 %0 %1}},
- OPCODE_OP_BOTTOM3,
- [[Eb,Gb],[Ev,Gv],
- [Gb,Eb],[Gv,Ev]]);
+ default: MultiInst::xor(OPCODE_OP_BOTTOM3,
+ [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]);
}
0x07: decode OPCODE_OP_BOTTOM3 {
0x0: cmp_Eb_Gb();
diff --git a/src/arch/x86/isa/formats/multi.isa b/src/arch/x86/isa/formats/multi.isa
index 9fceec2b0..7ad5ecd48 100644
--- a/src/arch/x86/isa/formats/multi.isa
+++ b/src/arch/x86/isa/formats/multi.isa
@@ -61,151 +61,26 @@
//
let {{
- # This builds either a regular or macro op to implement the sequence of
- # ops we give it.
- def genInst(name, Name, ops):
- # If we can implement this instruction with exactly one microop, just
- # use that directly.
- newStmnt = ''
- if len(ops) == 1:
- decode_block = "return (X86StaticInst *)(%s);" % \
- ops[0].getAllocator()
- return ('', '', decode_block, '')
- else:
- # Build a macroop to contain the sequence of microops we've
- # been given.
- return genMacroOp(name, Name, ops)
+ def doInst(name, Name, opTypeSet):
+ if not instDict.has_key(Name):
+ raise Exception, "Unrecognized instruction: %s" % Name
+ inst = instDict[Name]()
+ return inst.emit(opTypeSet)
}};
-let {{
- # This code builds up a decode block which decodes based on switchval.
- # vals is a dict which matches case values with what should be decoded to.
- # builder is called on the exploded contents of "vals" values to generate
- # whatever code should be used.
- def doMultiOp(name, Name, builder, switchVal, vals, default = None):
- header_output = ''
- decoder_output = ''
- decode_block = 'switch(%s) {\n' % switchVal
- exec_output = ''
- for (val, todo) in vals.items():
- (new_header_output,
- new_decoder_output,
- new_decode_block,
- new_exec_output) = builder(name, Name, *todo)
- header_output += new_header_output
- decoder_output += new_decoder_output
- decode_block += '\tcase %s: %s\n' % (val, new_decode_block)
- exec_output += new_exec_output
- if default:
- (new_header_output,
- new_decoder_output,
- new_decode_block,
- new_exec_output) = builder(name, Name, *default)
- header_output += new_header_output
- decoder_output += new_decoder_output
- decode_block += '\tdefault: %s\n' % new_decode_block
- exec_output += new_exec_output
- decode_block += '}\n'
- return (header_output, decoder_output, decode_block, exec_output)
-}};
-
-let {{
-
- # This function specializes the given piece of code to use a particular
- # set of argument types described by "opTags". These are "implemented"
- # in reverse order.
- def doCompOps(name, Name, code, opTags, postfix):
- opNum = len(opTags) - 1
- while len(opTags):
- # print "Building a composite op with tags", opTags
- # print "And code", code
- opNum = len(opTags) - 1
- # A regular expression to find the operand placeholders we're
- # interested in.
- opRe = re.compile("%%(?P<operandNum>%d)(?=[^0-9]|$)" % opNum)
- tag = opTags[opNum]
- # Build up a name for this instructions class using the argument
- # types. Each variation will get its own name this way.
- postfix = '_' + tag + postfix
- tagParser = re.compile(r"(?P<tagType>[A-Z][A-Z]*)(?P<tagSize>[a-z][a-z]*)|(r(?P<tagReg>[A-Za-z0-9][A-Za-z0-9]*))")
- tagMatch = tagParser.search(tag)
- if tagMatch == None:
- raise Exception, "Problem parsing operand tag %s" % tag
- reg = tagMatch.group("tagReg")
- tagType = tagMatch.group("tagType")
- tagSize = tagMatch.group("tagSize")
- if reg:
- #Figure out what to do with fixed register operands
- if reg in ("Ax", "Bx", "Cx", "Dx"):
- code = opRe.sub("{INTREG_R%s}" % reg.upper(), code)
- elif reg == "Al":
- # We need a way to specify register width
- code = opRe.sub("{INTREG_RAX}", code)
- else:
- print "Didn't know how to encode fixed register %s!" % reg
- elif tagType == None or tagSize == None:
- raise Exception, "Problem parsing operand tag: %s" % tag
- elif tagType == "C" or tagType == "D" or tagType == "G" or \
- tagType == "P" or tagType == "S" or \
- tagType == "T" or tagType == "V":
- # Use the "reg" field of the ModRM byte to select the register
- code = opRe.sub("{(uint8_t)MODRM_REG}", code)
- elif tagType == "E" or tagType == "Q" or tagType == "W":
- # This might refer to memory or to a register. We need to
- # divide it up farther.
- regCode = opRe.sub("{(uint8_t)MODRM_RM}", code)
- regTags = copy.copy(opTags)
- regTags.pop(-1)
- # This needs to refer to memory, but we'll fill in the details
- # later. It needs to take into account unaligned memory
- # addresses.
- memCode = opRe.sub("0", code)
- memTags = copy.copy(opTags)
- memTags.pop(-1)
- return doMultiOp(name, Name, doCompOps, "MODRM_MOD",
- {"3" : (regCode, regTags, postfix)},
- (memCode, memTags, postfix))
- elif tagType == "I" or tagType == "J":
- # Substitute in an immediate
- code = opRe.sub("{IMMEDIATE}", code)
- elif tagType == "M":
- # This needs to refer to memory, but we'll fill in the details
- # later. It needs to take into account unaligned memory
- # addresses.
- code = opRe.sub("0", code)
- elif tagType == "PR" or tagType == "R" or tagType == "VR":
- # There should probably be a check here to verify that mod
- # is equal to 11b
- code = opRe.sub("{(uint8_t)MODRM_RM}", code)
- else:
- raise Exception, "Unrecognized tag %s." % tag
- opTags.pop(-1)
-
- # At this point, we've built up "code" to have all the necessary extra
- # instructions needed to implement whatever types of operands were
- # specified. Now we'll assemble it it into a microOp sequence.
- ops = assembleMicro(code)
-
- # Build a macroop to contain the sequence of microops we've
- # constructed. The decode block will be used to fill in our
- # inner decode structure, and the rest will be concatenated and
- # passed back.
- return genInst(name, Name + postfix, ops)
-}};
-
-def format TaggedOp(code, tagSet) {{
+def format Inst(*opTypeSet) {{
(header_output,
decoder_output,
decode_block,
- exec_output) = doCompOps(name, Name, code, tagSet, '')
+ exec_output) = doInst(name, Name, list(opTypeSet))
}};
-def format MultiOp(code, switchVal, opTags, *opt_flags) {{
+def format MultiInst(switchVal, *opTypeSets) {{
switcher = {}
- for (count, tagSet) in zip(xrange(len(opTags) - 1), opTags):
- switcher[count] = (code, tagSet, '')
+ for (count, opTypeSet) in zip(xrange(len(opTypeSets)), opTypeSets):
+ switcher[count] = (opTypeSet,)
(header_output,
decoder_output,
decode_block,
- exec_output) = doMultiOp(name, Name, doCompOps, switchVal, switcher)
+ exec_output) = doSplitDecode(name, Name, doInst, switchVal, switcher)
}};
diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa
index fe1d4e515..cc3a9bee4 100644
--- a/src/arch/x86/isa/main.isa
+++ b/src/arch/x86/isa/main.isa
@@ -84,6 +84,9 @@ namespace X86ISA;
//Include the base class for x86 instructions, and some support code
##include "base.isa"
+//Include the instruction definitions
+##include "insts/insts.isa"
+
//Include the definitions for the instruction formats
##include "formats/formats.isa"
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 711ebf667..b94b55aab 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -57,11 +57,153 @@
////////////////////////////////////////////////////////////////////
//
-// Code to "assemble" microcode sequences
+// Code to "specialize" a microcode sequence to use a particular
+// variety of operands
//
let {{
- class MicroOpStatement:
+ # This builds either a regular or macro op to implement the sequence of
+ # ops we give it.
+ def genInst(name, Name, ops):
+ # If we can implement this instruction with exactly one microop, just
+ # use that directly.
+ newStmnt = ''
+ if len(ops) == 1:
+ decode_block = "return (X86StaticInst *)(%s);" % \
+ ops[0].getAllocator()
+ return ('', '', decode_block, '')
+ else:
+ # Build a macroop to contain the sequence of microops we've
+ # been given.
+ return genMacroOp(name, Name, ops)
+}};
+
+let {{
+ # This code builds up a decode block which decodes based on switchval.
+ # vals is a dict which matches case values with what should be decoded to.
+ # builder is called on the exploded contents of "vals" values to generate
+ # whatever code should be used.
+ def doSplitDecode(name, Name, builder, switchVal, vals, default = None):
+ header_output = ''
+ decoder_output = ''
+ decode_block = 'switch(%s) {\n' % switchVal
+ exec_output = ''
+ for (val, todo) in vals.items():
+ (new_header_output,
+ new_decoder_output,
+ new_decode_block,
+ new_exec_output) = builder(name, Name, *todo)
+ header_output += new_header_output
+ decoder_output += new_decoder_output
+ decode_block += '\tcase %s: %s\n' % (val, new_decode_block)
+ exec_output += new_exec_output
+ if default:
+ (new_header_output,
+ new_decoder_output,
+ new_decode_block,
+ new_exec_output) = builder(name, Name, *default)
+ header_output += new_header_output
+ decoder_output += new_decoder_output
+ decode_block += '\tdefault: %s\n' % new_decode_block
+ exec_output += new_exec_output
+ decode_block += '}\n'
+ return (header_output, decoder_output, decode_block, exec_output)
+}};
+
+let {{
+ class OpType(object):
+ parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Za-z0-9][A-Za-z0-9]*))")
+ def __init__(self, opTypeString):
+ match = OpType.parser.search(opTypeString)
+ if match == None:
+ raise Exception, "Problem parsing operand type %s" % opTypeString
+ self.reg = match.group("reg")
+ self.tag = match.group("tag")
+ self.size = match.group("size")
+}};
+
+let {{
+
+ # This function specializes the given piece of code to use a particular
+ # set of argument types described by "opTypes". These are "implemented"
+ # in reverse order.
+ def specializeInst(name, Name, code, opTypes):
+ opNum = len(opTypes) - 1
+ while len(opTypes):
+ # print "Building a composite op with tags", opTypes
+ # print "And code", code
+ opNum = len(opTypes) - 1
+ # A regular expression to find the operand placeholders we're
+ # interested in.
+ opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum)
+
+ # Parse the operand type strign we're working with
+ opType = OpType(opTypes[opNum])
+
+ if opType.reg:
+ #Figure out what to do with fixed register operands
+ if opType.reg in ("Ax", "Bx", "Cx", "Dx"):
+ code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code)
+ elif opType.reg == "Al":
+ # We need a way to specify register width
+ code = opRe.sub("%{INTREG_RAX}", code)
+ else:
+ print "Didn't know how to encode fixed register %s!" % opType.reg
+ elif opType.tag == None or opType.size == None:
+ raise Exception, "Problem parsing operand tag: %s" % opType.tag
+ elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
+ # Use the "reg" field of the ModRM byte to select the register
+ code = opRe.sub("%{(uint8_t)MODRM_REG}", code)
+ elif opType.tag in ("E", "Q", "W"):
+ # This might refer to memory or to a register. We need to
+ # divide it up farther.
+ regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code)
+ regTypes = copy.copy(opTypes)
+ regTypes.pop(-1)
+ # This needs to refer to memory, but we'll fill in the details
+ # later. It needs to take into account unaligned memory
+ # addresses.
+ memCode = opRe.sub("%0", code)
+ memTypes = copy.copy(opTypes)
+ memTypes.pop(-1)
+ return doSplitDecode(name, Name, specializeInst, "MODRM_MOD",
+ {"3" : (regCode, regTypes)}, (memCode, memTypes))
+ elif opType.tag in ("I", "J"):
+ # Immediates are already in the instruction, so don't leave in
+ # those parameters
+ code = opRe.sub("${IMMEDIATE}", code)
+ elif opType.tag == "M":
+ # This needs to refer to memory, but we'll fill in the details
+ # later. It needs to take into account unaligned memory
+ # addresses.
+ code = opRe.sub("%0", code)
+ elif opType.tag in ("PR", "R", "VR"):
+ # There should probably be a check here to verify that mod
+ # is equal to 11b
+ code = opRe.sub("%{(uint8_t)MODRM_RM}", code)
+ else:
+ raise Exception, "Unrecognized tag %s." % opType.tag
+ opTypes.pop(-1)
+
+ # At this point, we've built up "code" to have all the necessary extra
+ # instructions needed to implement whatever types of operands were
+ # specified. Now we'll assemble it it into a microOp sequence.
+ ops = assembleMicro(code)
+
+ # Build a macroop to contain the sequence of microops we've
+ # constructed. The decode block will be used to fill in our
+ # inner decode structure, and the rest will be concatenated and
+ # passed back.
+ return genInst(name, Name, ops)
+}};
+
+////////////////////////////////////////////////////////////////////
+//
+// The microcode assembler
+//
+
+let {{
+ class MicroOpStatement(object):
def __init__(self):
self.className = ''
self.label = ''
@@ -80,16 +222,24 @@ let {{
def getAllocator(self, *microFlags):
args = ''
+ signature = "<"
+ emptySig = True
for arg in self.args:
- if arg.has_key("operandConst"):
- args += ", %s" % arg["operandConst"]
- elif arg.has_key("operandCode"):
- args += ", %s" % arg["operandCode"]
+ if not emptySig:
+ signature += ", "
+ emptySig = False
+ if arg.has_key("operandImm"):
+ args += ", %s" % arg["operandImm"]
+ signature += ImmOpType
+ elif arg.has_key("operandReg"):
+ args += ", %s" % arg["operandReg"]
+ signature += RegOpType
elif arg.has_key("operandLabel"):
raise Exception, "Found a label while creating allocator string."
else:
raise Exception, "Unrecognized operand type."
- return 'new %s(machInst%s%s)' % (self.className, self.microFlagsText(microFlags), args)
+ signature += ">"
+ return 'new %s%s(machInst%s%s)' % (self.className, signature, self.microFlagsText(microFlags), args)
}};
let {{
@@ -101,7 +251,9 @@ let {{
labels[op.label] = count
micropc += 1
return labels
+}};
+let{{
def assembleMicro(code):
# This function takes in a block of microcode assembly and returns
# a python list of objects which describe it.
@@ -115,7 +267,7 @@ let {{
# time. Each expression expects the thing it's looking for to be at
# the beginning of the line, so the previous component is stripped
# before continuing.
- labelRe = re.compile(r'^[ \t]*(?P<label>[a-zA-Z_]\w*)[ \t]:')
+ labelRe = re.compile(r'^[ \t]*(?P<label>\w\w*)[ \t]:')
lineRe = re.compile(r'^(?P<line>[^\n][^\n]*)$')
classRe = re.compile(r'^[ \t]*(?P<className>[a-zA-Z_]\w*)')
# This recognizes three different flavors of operands:
@@ -126,7 +278,12 @@ let {{
# underscore, which is optionally followed by a sequence of
# capital or small letters, underscores, or digts between 0 and 9
opRe = re.compile( \
- r'^[ \t]*((?P<operandLabel>[a-zA-Z_]\w*)|(?P<operandConst>[0-9][0-9]*)|(\{(?P<operandCode>[^}]*)\}))')
+ r'^[ \t]*((\@(?P<operandLabel0>\w\w*))|' +
+ r'(\@\{(?P<operandLabel1>[^}]*)\})|' +
+ r'(\%(?P<operandReg0>\w\w*))|' +
+ r'(\%\{(?P<operandReg1>[^}]*)\})|' +
+ r'(\$(?P<operandImm0>\w\w*))|' +
+ r'(\$\{(?P<operandImm1>[^}]*)\}))')
lineMatch = lineRe.search(code)
while lineMatch != None:
statement = MicroOpStatement()
@@ -165,9 +322,10 @@ let {{
# representations of operand values. Different forms might be
# needed in different places, for instance to replace a label
# with an offset.
- for opType in ("operandLabel", "operandConst", "operandCode"):
+ for opType in ("operandLabel0", "operandReg0", "operandImm0",
+ "operandLabel1", "operandReg1", "operandImm1"):
if opMatch.group(opType):
- statement.args[-1][opType] = opMatch.group(opType)
+ statement.args[-1][opType[:-1]] = opMatch.group(opType)
if len(statement.args[-1]) == 0:
print "Problem parsing operand in statement: %s" \
% orig_line
@@ -193,7 +351,7 @@ let {{
# This is assuming that intra microcode branches go to
# the next micropc + displacement, or
# micropc + 1 + displacement.
- arg["operandConst"] = labels[arg["operandLabel"]] - micropc - 1
+ arg["operandImm"] = labels[arg["operandLabel"]] - micropc - 1
micropc += 1
return statements
}};
diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
new file mode 100644
index 000000000..b1351d999
--- /dev/null
+++ b/src/arch/x86/isa/microops/base.isa
@@ -0,0 +1,172 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//The operand types a microop template can be specialized with
+output header {{
+ enum OperandType {
+ RegisterOperand,
+ ImmediateOperand
+ };
+}};
+
+//A class which is the base of all x86 micro ops it provides a function to
+//set necessary flags appropriately.
+output header {{
+ class X86MicroOpBase : public X86StaticInst
+ {
+ protected:
+ X86MicroOpBase(bool isMicro, bool isDelayed,
+ bool isFirst, bool isLast,
+ const char *mnem, ExtMachInst _machInst,
+ OpClass __opClass) :
+ X86StaticInst(mnem, _machInst, __opClass)
+ {
+ flags[IsMicroOp] = isMicro;
+ flags[IsDelayedCommit] = isDelayed;
+ flags[IsFirstMicroOp] = isFirst;
+ flags[IsLastMicroOp] = isLast;
+ }
+ };
+}};
+
+// This sets up a class which is templated on the type of
+// arguments a particular flavor of a microcode instruction
+// can accept. It's parameters are specialized to create polymorphic
+// behavior in microops.
+def template BaseMicroOpTemplateDeclare {{
+ template%(signature)s
+ class %(class_name)s;
+}};
+
+let {{
+ def buildBaseMicroOpTemplate(Name, numParams):
+ signature = "<"
+ signature += "int SignatureOperandTypeSpecifier0"
+ for count in xrange(1,numParams):
+ signature += \
+ ", int SingatureOperandTypeSpecifier%d" % count
+ signature += ">"
+ subs = {"signature" : signature, "class_name" : Name}
+ return BaseMicroOpTemplateDeclare.subst(subs)
+
+ RegOpType = "RegisterOperand"
+ ImmOpType = "ImmediateOperand"
+
+ def buildMicroOpTemplateDict(*params):
+ signature = "<"
+ if len(params):
+ signature += params[0]
+ if len(params) > 1:
+ for param in params[1:]:
+ signature += ", %s" % param
+ signature += ">"
+ subs = {"param_dec" : "", "param_arg_dec" : "",
+ "param_init" : "", "signature" : signature}
+ for count in xrange(len(params)):
+ subs["param_dec"] += "uint64_t param%d;\n" % count
+ subs["param_arg_dec"] += ", uint64_t _param%d" % count
+ subs["param_init"] += ", param%d(_param%d)" % (count, count)
+ return subs
+}};
+
+// A tmeplate for building a specialized version of the microcode
+// instruction which knows specifies which arguments it wants
+def template MicroOpDeclare {{
+ template<>
+ class %(class_name)s%(signature)s : public X86MicroOpBase
+ {
+ protected:
+ %(param_dec)s
+ void buildMe();
+
+ public:
+ %(class_name)s(bool isMicro, bool isDelayed,
+ bool isFirst, bool isLast,
+ ExtMachInst _machInst %(param_arg_dec)s);
+
+ %(class_name)s(ExtMachInst _machInst %(param_arg_dec)s);
+
+ %(BasicExecDeclare)s
+ };
+}};
+
+def template MicroOpConstructor {{
+
+ inline void %(class_name)s%(signature)s::buildMe()
+ {
+ %(constructor)s;
+ }
+
+ inline %(class_name)s%(signature)s::%(class_name)s(
+ ExtMachInst machInst %(param_arg_dec)s) :
+ %(base_class)s(false, false, false, false,
+ "%(mnemonic)s", machInst, %(op_class)s)
+ %(param_init)s
+ {
+ buildMe();
+ }
+
+ inline %(class_name)s%(signature)s::%(class_name)s(
+ bool isMicro, bool isDelayed, bool isFirst, bool isLast,
+ ExtMachInst machInst %(param_arg_dec)s)
+ : %(base_class)s(isMicro, isDelayed, isFirst, isLast,
+ "%(mnemonic)s", machInst, %(op_class)s)
+ %(param_init)s
+ {
+ buildMe();
+ }
+}};
diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa
index bbf26f605..bb136fc81 100644
--- a/src/arch/x86/isa/microops/microops.isa
+++ b/src/arch/x86/isa/microops/microops.isa
@@ -53,5 +53,8 @@
//
// Authors: Gabe Black
-//Micro ops
+//Common microop stuff
+##include "base.isa"
+
+//Integer microop definitions
##include "int.isa"
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 36b0ee4df..af469ab3d 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,7 +96,7 @@ def operand_types {{
}};
def operands {{
- 'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
- 'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
- 'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
+ 'IntRegOp0': ('IntReg', 'udw', 'param0', 'IsInteger', 1),
+ 'IntRegOp1': ('IntReg', 'udw', 'param1', 'IsInteger', 2),
+ 'IntRegOp2': ('IntReg', 'udw', 'param2', 'IsInteger', 2),
}};
diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh
index ca4a15d24..cdac3c00e 100644
--- a/src/arch/x86/types.hh
+++ b/src/arch/x86/types.hh
@@ -161,7 +161,26 @@ namespace X86ISA
inline static bool
operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
{
- //Since this is empty, it's always equal
+ if(emi1.legacy != emi2.legacy)
+ return false;
+ if(emi1.rex != emi2.rex)
+ return false;
+ if(emi1.opcode.num != emi2.opcode.num)
+ return false;
+ if(emi1.opcode.op != emi2.opcode.op)
+ return false;
+ if(emi1.opcode.prefixA != emi2.opcode.prefixA)
+ return false;
+ if(emi1.opcode.prefixB != emi2.opcode.prefixB)
+ return false;
+ if(emi1.modRM != emi2.modRM)
+ return false;
+ if(emi1.sib != emi2.sib)
+ return false;
+ if(emi1.immediate != emi2.immediate)
+ return false;
+ if(emi1.displacement != emi2.displacement)
+ return false;
return true;
}
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index d89e223de..e0bd09515 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -70,8 +70,15 @@ namespace __hash_namespace {
template<>
struct hash<X86ISA::ExtMachInst> {
size_t operator()(const X86ISA::ExtMachInst &emi) const {
- //Because these are all the same, return 0
- return 0;
+ return (((uint64_t)emi.legacy << 56) |
+ ((uint64_t)emi.rex << 48) |
+ ((uint64_t)emi.modRM << 40) |
+ ((uint64_t)emi.sib << 32) |
+ ((uint64_t)emi.opcode.num << 24) |
+ ((uint64_t)emi.opcode.prefixA << 16) |
+ ((uint64_t)emi.opcode.prefixB << 8) |
+ ((uint64_t)emi.opcode.op)) ^
+ emi.immediate ^ emi.displacement;
};
};
}