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authorAndreas Hansson <andreas.hansson@arm.com>2016-01-11 05:52:20 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2016-01-11 05:52:20 -0500
commit12eb0343784f52994110df7e7fce4a0b639a6ec3 (patch)
tree12ff1c51b8051bb7e7d889eed499bee0dcd4cd1e /src
parent7661f1c2bf2b45603264076fabce2eb42373cd18 (diff)
downloadgem5-12eb0343784f52994110df7e7fce4a0b639a6ec3.tar.xz
scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial.
Diffstat (limited to 'src')
-rwxr-xr-xsrc/SConscript18
-rw-r--r--src/arch/alpha/faults.hh2
-rw-r--r--src/arch/alpha/utility.hh2
-rw-r--r--src/arch/arm/faults.hh2
-rw-r--r--src/arch/arm/utility.cc2
-rw-r--r--src/arch/mips/faults.hh2
-rw-r--r--src/arch/mips/isa/decoder.isa4
-rw-r--r--src/arch/sparc/isa/decoder.isa16
-rw-r--r--src/base/bitunion.hh12
-rw-r--r--src/cpu/base_dyn_inst.hh6
-rw-r--r--src/cpu/pred/sat_counter.hh2
-rw-r--r--src/cpu/trace/trace_cpu.cc4
-rw-r--r--src/dev/arm/hdlcd.hh2
-rw-r--r--src/dev/arm/pl011.hh2
-rw-r--r--src/dev/net/ethertap.cc2
-rw-r--r--src/dev/net/ns_gige_reg.h3
-rw-r--r--src/dev/net/pktfifo.hh2
-rw-r--r--src/dev/sparc/iob.cc6
-rw-r--r--src/dev/terminal.cc2
-rw-r--r--src/mem/packet.hh2
-rw-r--r--src/mem/page_table.hh1
-rw-r--r--src/mem/request.hh1
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh4
-rw-r--r--src/mem/ruby/slicc_interface/Message.hh6
-rw-r--r--src/mem/ruby/structures/RubyMemoryControl.cc10
-rw-r--r--src/mem/ruby/structures/RubyMemoryControl.hh10
-rw-r--r--src/mem/ruby/system/RubySystem.hh2
-rw-r--r--src/sim/process.cc5
-rw-r--r--src/sim/sim_events.hh6
29 files changed, 67 insertions, 71 deletions
diff --git a/src/SConscript b/src/SConscript
index eae03a98a..322212cb7 100755
--- a/src/SConscript
+++ b/src/SConscript
@@ -1018,11 +1018,6 @@ def makeEnv(env, label, objsfx, strip = False, **kwargs):
# the SWIG generated code
swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value'])
- # Add additional warnings here that should not be applied to
- # the SWIG generated code
- new_env.Append(CXXFLAGS=['-Wmissing-declarations',
- '-Wdelete-non-virtual-dtor'])
-
if env['GCC']:
# Depending on the SWIG version, we also need to supress
# warnings about uninitialized variables and missing field
@@ -1030,7 +1025,8 @@ def makeEnv(env, label, objsfx, strip = False, **kwargs):
swig_env.Append(CCFLAGS=['-Wno-uninitialized',
'-Wno-missing-field-initializers',
'-Wno-unused-but-set-variable',
- '-Wno-maybe-uninitialized'])
+ '-Wno-maybe-uninitialized',
+ '-Wno-type-limits'])
# Only gcc >= 4.9 supports UBSan, so check both the version
# and the command-line option before adding the compiler and
@@ -1041,13 +1037,9 @@ def makeEnv(env, label, objsfx, strip = False, **kwargs):
new_env.Append(LINKFLAGS='-fsanitize=undefined')
if env['CLANG']:
- swig_env.Append(CCFLAGS=[
- # Some versions of SWIG can return uninitialized values
- '-Wno-sometimes-uninitialized',
- # Register storage is requested in a lot of places in
- # SWIG-generated code.
- '-Wno-deprecated-register',
- ])
+ swig_env.Append(CCFLAGS=['-Wno-sometimes-uninitialized',
+ '-Wno-deprecated-register',
+ '-Wno-tautological-compare'])
# All supported clang versions have support for UBSan, so if
# asked to use it, append the compiler and linker flags.
diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 005d8af8a..80e3ae5e1 100644
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -40,7 +40,7 @@
namespace AlphaISA {
-typedef const Addr FaultVect;
+typedef Addr FaultVect;
class AlphaFault : public FaultBase
{
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a52125066..45e47b5e8 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -78,7 +78,7 @@ inline void startupCPU(ThreadContext *tc, int cpuId)
inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
// User Virtual
-inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
+inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
// Kernel Direct Mapped
inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index ef87ee145..02d2e81f5 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -58,7 +58,7 @@
namespace ArmISA
{
-typedef const Addr FaultOffset;
+typedef Addr FaultOffset;
class ArmFault : public FaultBase
{
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index bedd4a0b0..a4ae849c1 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -209,7 +209,7 @@ getMPIDR(ArmSystem *arm_sys, ThreadContext *tc)
// We deliberately extend both the Cluster ID and CPU ID fields to allow
// for simulation of larger systems
assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
- assert((0 <= tc->socketId()) && (tc->socketId() < 65536));
+ assert(tc->socketId() < 65536);
if (arm_sys->multiThread) {
return 0x80000000 | // multiprocessor extensions available
tc->contextId();
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index d843acc50..1ec726d17 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -45,7 +45,7 @@
namespace MipsISA
{
-typedef const Addr FaultVect;
+typedef Addr FaultVect;
enum ExcCode {
// A dummy value to use when the code isn't defined or doesn't matter.
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index a62dbb7bb..52cbc4041 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -2404,7 +2404,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode OP_LO {
format DspHiLoOp {
0x2: shilo({{
- if (sext<6>(HILOSA) < 0) {
+ if ((int64_t)sext<6>(HILOSA) < 0) {
dspac = (uint64_t)dspac <<
-sext<6>(HILOSA);
} else {
@@ -2413,7 +2413,7 @@ decode OPCODE_HI default Unknown::unknown() {
}
}});
0x3: shilov({{
- if (sext<6>(Rs_sw<5:0>) < 0) {
+ if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) {
dspac = (uint64_t)dspac <<
-sext<6>(Rs_sw<5:0>);
} else {
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index befac53e6..492e1a00a 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -669,13 +669,13 @@ decode OP default Unknown::unknown()
}});
0x43: FpUnimpl::fmovq_fcc1();
0x45: fmovrslez({{
- if (Rs1 <= 0)
+ if ((int64_t)Rs1 <= 0)
Frds = Frs2s;
else
Frds = Frds;
}});
0x46: fmovrdlez({{
- if (Rs1 <= 0)
+ if ((int64_t)Rs1 <= 0)
Frd = Frs2;
else
Frd = Frd;
@@ -740,13 +740,13 @@ decode OP default Unknown::unknown()
}});
0x57: FpUnimpl::fcmpeq();
0x65: fmovrslz({{
- if (Rs1 < 0)
+ if ((int64_t)Rs1 < 0)
Frds = Frs2s;
else
Frds = Frds;
}});
0x66: fmovrdlz({{
- if (Rs1 < 0)
+ if ((int64_t)Rs1 < 0)
Frd = Frs2;
else
Frd = Frd;
@@ -792,26 +792,26 @@ decode OP default Unknown::unknown()
}});
0xC3: FpUnimpl::fmovq_fcc3();
0xC5: fmovrsgz({{
- if (Rs1 > 0)
+ if ((int64_t)Rs1 > 0)
Frds = Frs2s;
else
Frds = Frds;
}});
0xC6: fmovrdgz({{
- if (Rs1 > 0)
+ if ((int64_t)Rs1 > 0)
Frd = Frs2;
else
Frd = Frd;
}});
0xC7: FpUnimpl::fmovrqgz();
0xE5: fmovrsgez({{
- if (Rs1 >= 0)
+ if ((int64_t)Rs1 >= 0)
Frds = Frs2s;
else
Frds = Frds;
}});
0xE6: fmovrdgez({{
- if (Rs1 >= 0)
+ if ((int64_t)Rs1 >= 0)
Frd = Frs2;
else
Frd = Frd;
diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index c4b67b073..35448ed24 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -89,7 +89,7 @@ namespace BitfieldBackend
"Bitfield ranges must be specified as <msb, lsb>");
public:
- operator const uint64_t () const
+ operator uint64_t () const
{
return this->getBits(first, last);
}
@@ -129,7 +129,7 @@ namespace BitfieldBackend
class BitfieldWO : public Bitfield<first, last>
{
private:
- operator const uint64_t () const;
+ operator uint64_t () const;
public:
using Bitfield<first, last>::operator=;
@@ -148,7 +148,7 @@ namespace BitfieldBackend
class SignedBitfield : public BitfieldBase<Type>
{
public:
- operator const int64_t () const
+ operator int64_t () const
{
return sext<first - last + 1>(this->getBits(first, last));
}
@@ -188,7 +188,7 @@ namespace BitfieldBackend
class SignedBitfieldWO : public SignedBitfield<first, last>
{
private:
- operator const int64_t () const;
+ operator int64_t () const;
public:
using SignedBitfield<first, last>::operator=;
@@ -304,10 +304,10 @@ namespace BitfieldBackend
//do so.
#define EndSubBitUnion(name) \
}; \
- inline operator const __DataType () const \
+ inline operator __DataType () const \
{ return __data; } \
\
- inline const __DataType operator = (const __DataType & _data) \
+ inline __DataType operator = (const __DataType & _data) \
{ return __data = _data;} \
} name;
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 77117b892..ebe882a88 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -793,13 +793,13 @@ class BaseDynInst : public ExecContext, public RefCounted
void pcState(const TheISA::PCState &val) { pc = val; }
/** Read the PC of this instruction. */
- const Addr instAddr() const { return pc.instAddr(); }
+ Addr instAddr() const { return pc.instAddr(); }
/** Read the PC of the next instruction. */
- const Addr nextInstAddr() const { return pc.nextInstAddr(); }
+ Addr nextInstAddr() const { return pc.nextInstAddr(); }
/**Read the micro PC of this instruction. */
- const Addr microPC() const { return pc.microPC(); }
+ Addr microPC() const { return pc.microPC(); }
bool readPredicate()
{
diff --git a/src/cpu/pred/sat_counter.hh b/src/cpu/pred/sat_counter.hh
index 1294a4e08..4721a3f9f 100644
--- a/src/cpu/pred/sat_counter.hh
+++ b/src/cpu/pred/sat_counter.hh
@@ -105,7 +105,7 @@ class SatCounter
/**
* Read the counter's value.
*/
- const uint8_t read() const
+ uint8_t read() const
{ return counter; }
private:
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index f940be2f9..d6aa9aaeb 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -1337,8 +1337,8 @@ TraceCPU::ElasticDataGen::GraphNode::removeRegDep(NodeSeqNum reg_dep)
if (own_reg_dep == reg_dep) {
// If register dependency is found, make it zero and return true
own_reg_dep = 0;
+ assert(numRegDep > 0);
--numRegDep;
- assert(numRegDep >= 0);
DPRINTFR(TraceCPUData, "\tFor %lli: Marking register dependency %lli "
"done.\n", seqNum, reg_dep);
return true;
@@ -1356,8 +1356,8 @@ TraceCPU::ElasticDataGen::GraphNode::removeRobDep(NodeSeqNum rob_dep)
if (own_rob_dep == rob_dep) {
// If the rob dependency is found, make it zero and return true
own_rob_dep = 0;
+ assert(numRobDep > 0);
--numRobDep;
- assert(numRobDep >= 0);
DPRINTFR(TraceCPUData, "\tFor %lli: Marking ROB dependency %lli "
"done.\n", seqNum, rob_dep);
return true;
diff --git a/src/dev/arm/hdlcd.hh b/src/dev/arm/hdlcd.hh
index 3ce12a24d..721935457 100644
--- a/src/dev/arm/hdlcd.hh
+++ b/src/dev/arm/hdlcd.hh
@@ -316,7 +316,7 @@ class HDLcd: public AmbaDmaDevice
}
/** Masked interrupt status register */
- const uint32_t intStatus() const { return int_rawstat & int_mask; }
+ uint32_t intStatus() const { return int_rawstat & int_mask; }
protected: // Pixel output
class PixelPump : public BasePixelPump
diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index 936dd81ed..e19c74fa2 100644
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -110,7 +110,7 @@ class Pl011 : public Uart, public AmbaDevice
void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); }
/** Masked interrupt status register */
- const inline uint16_t maskInt() const { return rawInt & imsc; }
+ inline uint16_t maskInt() const { return rawInt & imsc; }
/** Wrapper to create an event out of the thing */
EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
diff --git a/src/dev/net/ethertap.cc b/src/dev/net/ethertap.cc
index e8d6a363c..e8ece152e 100644
--- a/src/dev/net/ethertap.cc
+++ b/src/dev/net/ethertap.cc
@@ -241,8 +241,8 @@ EtherTap::process(int revent)
packet->length = data_len;
memcpy(packet->data, data, data_len);
+ assert(buffer_offset >= data_len + sizeof(uint32_t));
buffer_offset -= data_len + sizeof(uint32_t);
- assert(buffer_offset >= 0);
if (buffer_offset > 0) {
memmove(buffer, data + data_len, buffer_offset);
data_len = ntohl(*(uint32_t *)buffer);
diff --git a/src/dev/net/ns_gige_reg.h b/src/dev/net/ns_gige_reg.h
index c37c06aed..4cecbb158 100644
--- a/src/dev/net/ns_gige_reg.h
+++ b/src/dev/net/ns_gige_reg.h
@@ -93,6 +93,7 @@ enum ChipCommandRegister {
/* configuration register */
enum ConfigurationRegisters {
+ CFGR_ZERO = 0x00000000,
CFGR_LNKSTS = 0x80000000,
CFGR_SPDSTS = 0x60000000,
CFGR_SPDSTS1 = 0x40000000,
@@ -395,7 +396,7 @@ static inline int
SPDSTS_POLARITY(int lnksts)
{
return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
- (lnksts ? CFGR_LNKSTS : 0));
+ (lnksts ? CFGR_LNKSTS : CFGR_ZERO));
}
#endif /* __DEV_NS_GIGE_REG_H__ */
diff --git a/src/dev/net/pktfifo.hh b/src/dev/net/pktfifo.hh
index 5ef75423c..456c4433b 100644
--- a/src/dev/net/pktfifo.hh
+++ b/src/dev/net/pktfifo.hh
@@ -106,8 +106,8 @@ class PacketFifo
unsigned
reserve(unsigned len = 0)
{
+ assert(avail() >= len);
_reserved += len;
- assert(avail() >= 0);
return _reserved;
}
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index c8462b9be..55cb93f37 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -91,7 +91,8 @@ Iob::readIob(PacketPtr pkt)
{
Addr accessAddr = pkt->getAddr() - iobManAddr;
- if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
+ assert(IntManAddr == 0);
+ if (accessAddr < IntManAddr + IntManSize) {
int index = (accessAddr - IntManAddr) >> 3;
uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
pkt->set(data);
@@ -186,7 +187,8 @@ Iob::writeIob(PacketPtr pkt)
int index;
uint64_t data;
- if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) {
+ assert(IntManAddr == 0);
+ if (accessAddr < IntManAddr + IntManSize) {
index = (accessAddr - IntManAddr) >> 3;
data = pkt->get<uint64_t>();
intMan[index].cpu = bits(data,12,8);
diff --git a/src/dev/terminal.cc b/src/dev/terminal.cc
index e653ee115..6db43ef88 100644
--- a/src/dev/terminal.cc
+++ b/src/dev/terminal.cc
@@ -249,7 +249,7 @@ Terminal::read(uint8_t *buf, size_t len)
if (data_fd < 0)
panic("Terminal not properly attached.\n");
- size_t ret;
+ ssize_t ret;
do {
ret = ::read(data_fd, buf, len);
} while (ret == -1 && errno == EINTR);
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 32c4cf631..0e7135d73 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -215,7 +215,7 @@ class MemCmd
bool isPrint() const { return testCmdAttrib(IsPrint); }
bool isFlush() const { return testCmdAttrib(IsFlush); }
- const Command
+ Command
responseCommand() const
{
return commandInfo[cmd].response;
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 47c7c5491..645548263 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -93,6 +93,7 @@ class PageTableBase : public Serializable
* bit 3 - read-write | read-only
*/
enum MappingFlags : uint32_t {
+ Zero = 0,
Clobber = 1,
NotPresent = 2,
Uncacheable = 4,
diff --git a/src/mem/request.hh b/src/mem/request.hh
index ef58686d6..de781f5d6 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -234,7 +234,6 @@ class Request
void
setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time)
{
- assert(size >= 0);
_paddr = paddr;
_size = size;
_time = time;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 34160c149..383507eed 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -65,8 +65,8 @@ class AbstractController : public MemObject, public Consumer
void init();
const Params *params() const { return (const Params *)_params; }
- const NodeID getVersion() const { return m_machineID.getNum(); }
- const MachineType getType() const { return m_machineID.getType(); }
+ NodeID getVersion() const { return m_machineID.getNum(); }
+ MachineType getType() const { return m_machineID.getType(); }
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh
index 587103101..c62b4e123 100644
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -83,12 +83,12 @@ class Message
Tick delta = curTime - m_LastEnqueueTime;
m_DelayedTicks += delta;
}
- const Tick getDelayedTicks() const {return m_DelayedTicks;}
+ Tick getDelayedTicks() const {return m_DelayedTicks;}
void setLastEnqueueTime(const Tick& time) { m_LastEnqueueTime = time; }
- const Tick getLastEnqueueTime() const {return m_LastEnqueueTime;}
+ Tick getLastEnqueueTime() const {return m_LastEnqueueTime;}
- const Tick& getTime() const { return m_time; }
+ Tick getTime() const { return m_time; }
void setMsgCounter(uint64_t c) { m_msg_counter = c; }
uint64_t getMsgCounter() const { return m_msg_counter; }
diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc
index 5feb9348b..77f1c239f 100644
--- a/src/mem/ruby/structures/RubyMemoryControl.cc
+++ b/src/mem/ruby/structures/RubyMemoryControl.cc
@@ -342,7 +342,7 @@ RubyMemoryControl::enqueueToDirectory(MemoryNode *req, Cycles latency)
// getBank returns an integer that is unique for each
// bank across this memory controller.
-const int
+int
RubyMemoryControl::getBank(const Addr addr) const
{
int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1);
@@ -353,7 +353,7 @@ RubyMemoryControl::getBank(const Addr addr) const
+ bank;
}
-const int
+int
RubyMemoryControl::getRank(const Addr addr) const
{
int bank = getBank(addr);
@@ -364,7 +364,7 @@ RubyMemoryControl::getRank(const Addr addr) const
// getRank returns an integer that is unique for each rank
// and independent of individual bank.
-const int
+int
RubyMemoryControl::getRank(int bank) const
{
int rank = (bank / m_banks_per_rank);
@@ -373,7 +373,7 @@ RubyMemoryControl::getRank(int bank) const
}
// Not used!
-const int
+int
RubyMemoryControl::getChannel(const Addr addr) const
{
assert(false);
@@ -381,7 +381,7 @@ RubyMemoryControl::getChannel(const Addr addr) const
}
// Not used!
-const int
+int
RubyMemoryControl::getRow(const Addr addr) const
{
assert(false);
diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh
index cd777f5e7..601c4d1a2 100644
--- a/src/mem/ruby/structures/RubyMemoryControl.hh
+++ b/src/mem/ruby/structures/RubyMemoryControl.hh
@@ -75,12 +75,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
void print(std::ostream& out) const override;
void regStats() override;
- const int getBank(const Addr addr) const;
- const int getRank(const Addr addr) const;
+ int getBank(const Addr addr) const;
+ int getRank(const Addr addr) const;
// not used in Ruby memory controller
- const int getChannel(const Addr addr) const;
- const int getRow(const Addr addr) const;
+ int getChannel(const Addr addr) const;
+ int getRow(const Addr addr) const;
//added by SS
int getBanksPerRank() { return m_banks_per_rank; };
@@ -92,7 +92,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer
private:
void enqueueToDirectory(MemoryNode *req, Cycles latency);
- const int getRank(int bank) const;
+ int getRank(int bank) const;
bool queueReady(int bank);
void issueRequest(int bank);
bool issueRefresh(int bank);
diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh
index e396dce64..62330e19d 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -79,7 +79,7 @@ class RubySystem : public ClockedObject
SimpleMemory *getPhysMem() { return m_phys_mem; }
Cycles getStartCycle() { return m_start_cycle; }
- const bool getAccessBackingStore() { return m_access_backing_store; }
+ bool getAccessBackingStore() { return m_access_backing_store; }
// Public Methods
Profiler*
diff --git a/src/sim/process.cc b/src/sim/process.cc
index cbafb62fe..0107f63a2 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -290,7 +290,8 @@ Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
int npages = divCeil(size, (int64_t)PageBytes);
Addr paddr = system->allocPhysPages(npages);
- pTable->map(vaddr, paddr, size, clobber ? PageTableBase::Clobber : 0);
+ pTable->map(vaddr, paddr, size,
+ clobber ? PageTableBase::Clobber : PageTableBase::Zero);
}
bool
@@ -454,7 +455,7 @@ bool
Process::map(Addr vaddr, Addr paddr, int size, bool cacheable)
{
pTable->map(vaddr, paddr, size,
- cacheable ? 0 : PageTableBase::Uncacheable);
+ cacheable ? PageTableBase::Zero : PageTableBase::Uncacheable);
return true;
}
diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh
index 9a79a2e9d..8fb04408a 100644
--- a/src/sim/sim_events.hh
+++ b/src/sim/sim_events.hh
@@ -66,7 +66,7 @@ class GlobalSimLoopExitEvent : public GlobalEvent
Tick repeat = 0);
const std::string getCause() const { return cause; }
- const int getCode() const { return code; }
+ int getCode() const { return code; }
void process(); // process event
@@ -86,7 +86,7 @@ class LocalSimLoopExitEvent : public Event
LocalSimLoopExitEvent(const std::string &_cause, int c, Tick repeat = 0);
const std::string getCause() const { return cause; }
- const int getCode() const { return code; }
+ int getCode() const { return code; }
void process() override; // process event
@@ -111,7 +111,7 @@ class CountedDrainEvent : public Event
void setCount(int _count) { count = _count; }
- const int getCount() const { return count; }
+ int getCount() const { return count; }
};
//