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authorIru Cai <mytbk920423@gmail.com>2019-04-08 11:32:47 +0800
committerIru Cai <mytbk920423@gmail.com>2019-04-08 11:32:47 +0800
commit150bc41ca61a75b6df996395a649a331ef3b049a (patch)
treeeea3d3343c1c1a15097e86ff969d031b2771c38e /src
parentb6141109804bf4637345d5b8079c9a6debee285c (diff)
downloadgem5-150bc41ca61a75b6df996395a649a331ef3b049a.tar.xz
we need to ++loadsToVLD when (!inst->readyToExpose() && inst->needPostFetch())
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 3edbe4761..e31532d48 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1062,6 +1062,9 @@ LSQUnit<Impl>::updateVisibleState()
inst->readyToExpose(false);
} else {
DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState());
+ if (!inst->readyToExpose() && inst->needPostFetch()) {
+ ++loadsToVLD;
+ }
inst->readyToExpose(true);
}
}
@@ -1086,6 +1089,8 @@ LSQUnit<Impl>::exposeLoads()
int old_loadsToVLD = loadsToVLD;
+ DPRINTF(LSQUnit, "starting exposeLoads(): loadsToVLD = %d\n", loadsToVLD);
+
// [InvisiSpec] Note:
// need to iterate from the head every time
// since the load can be exposed out-of-order