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authorAli Saidi <Ali.Saidi@ARM.com>2011-02-23 15:10:48 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2011-02-23 15:10:48 -0600
commit2157b9976b55a6f3c25bbb788cdde931092aad3d (patch)
tree4c19bf2700cbf92235322911f16533cdd2d04d0f /src
parentd63020717c8a722eb2f5236eacd042cdee78769d (diff)
downloadgem5-2157b9976b55a6f3c25bbb788cdde931092aad3d.tar.xz
ARM: Reset simulation statistics when pref counters are reset.
The ARM performance counters are not currently supported by the model. This patch interprets a 'reset performance counters' command to mean 'reset the simulator statistics' instead.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 649394270..4bdbe77ce 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -40,6 +40,7 @@
#include "arch/arm/isa.hh"
#include "sim/faults.hh"
+#include "sim/stat_control.hh"
namespace ArmISA
{
@@ -393,6 +394,18 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
warn("Not doing anything for write of miscreg ACTLR\n");
break;
case MISCREG_PMCR:
+ {
+ // Performance counters not implemented. Instead, interpret
+ // a reset command to this register to reset the simulator
+ // statistics.
+ // PMCR_E | PMCR_P | PMCR_C
+ const int ResetAndEnableCounters = 0x7;
+ if (newVal == ResetAndEnableCounters) {
+ inform("Resetting all simobject stats\n");
+ Stats::schedStatEvent(false, true);
+ break;
+ }
+ }
case MISCREG_PMCCNTR:
case MISCREG_PMSELR:
warn("Not doing anything for write to miscreg %s\n",