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authorGabe Black <gblack@eecs.umich.edu>2007-03-11 18:12:33 -0400
committerGabe Black <gblack@eecs.umich.edu>2007-03-11 18:12:33 -0400
commit26c0426e443c34c1264ea437692a85a3f0967614 (patch)
tree28e32799d450e34ba0c6431613c26f0eafa3b7fb /src
parent78cf033dc0041fe7298765732b26c00a9732ccc5 (diff)
downloadgem5-26c0426e443c34c1264ea437692a85a3f0967614.tar.xz
Make sttw and sttwa use the twin memory operations.
--HG-- extra : convert_revision : 368d1c57a46fd5ca15461cb5ee8e05fd1e080daa
Diffstat (limited to 'src')
-rw-r--r--src/arch/sparc/isa/decoder.isa10
-rw-r--r--src/arch/sparc/isa/formats/mem/util.isa4
-rw-r--r--src/base/bigint.hh14
-rw-r--r--src/cpu/simple/atomic.cc11
-rw-r--r--src/cpu/simple/timing.cc10
5 files changed, 45 insertions, 4 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 04534cb34..0edb959f0 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1320,7 +1320,10 @@ decode OP default Unknown::unknown()
0x04: stw({{Mem.uw = Rd.sw;}});
0x05: stb({{Mem.ub = Rd.sb;}});
0x06: sth({{Mem.uhw = Rd.shw;}});
- 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
+ 0x07: sttw({{
+ (Mem.tuw).a = RdLow<31:0>;
+ (Mem.tuw).b = RdHigh<31:0>;
+ }});
}
format Load {
0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
@@ -1410,7 +1413,10 @@ decode OP default Unknown::unknown()
0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
- 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
+ 0x17: sttwa({{
+ (Mem.tuw).a = RdLow<31:0>;
+ (Mem.tuw).b = RdHigh<31:0>;
+ }}, {{EXT_ASI}});
}
format LoadAlt {
0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 1d884d6c3..dfe937371 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -224,7 +224,7 @@ def template StoreExecute {{
}
if(storeCond && fault == NoFault)
{
- fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
@@ -257,7 +257,7 @@ def template StoreInitiateAcc {{
}
if(storeCond && fault == NoFault)
{
- fault = xc->write((uint%(mem_acc_size)s_t)Mem,
+ fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
EA, %(asi_val)s, 0);
}
if(fault == NoFault)
diff --git a/src/base/bigint.hh b/src/base/bigint.hh
index ed48c67fe..d60684231 100644
--- a/src/base/bigint.hh
+++ b/src/base/bigint.hh
@@ -28,6 +28,8 @@
* Authors: Ali Saidi
*/
+#include "base/misc.hh"
+
#include <iostream>
#ifndef __BASE_BIGINT_HH__
@@ -49,6 +51,12 @@ struct m5_twin64_t {
b = x;
return *this;
}
+
+ operator uint64_t()
+ {
+ panic("Tried to cram a twin64_t into an integer!\n");
+ return a;
+ }
};
struct m5_twin32_t {
@@ -67,6 +75,12 @@ struct m5_twin32_t {
b = x;
return *this;
}
+
+ operator uint32_t()
+ {
+ panic("Tried to cram a twin32_t into an integer!\n");
+ return a;
+ }
};
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ca4627bbf..6a14a8aa5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -446,6 +446,17 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+AtomicSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
template
Fault
AtomicSimpleCPU::write(uint64_t data, Addr addr,
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2e602648a..45da7c3eb 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -398,6 +398,16 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
#ifndef DOXYGEN_SHOULD_SKIP_THIS
template
Fault
+TimingSimpleCPU::write(Twin32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(Twin64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
TimingSimpleCPU::write(uint64_t data, Addr addr,
unsigned flags, uint64_t *res);