summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorIru Cai <mytbk920423@gmail.com>2019-04-17 10:54:51 +0800
committerIru Cai <mytbk920423@gmail.com>2019-04-17 10:54:51 +0800
commit30488f4a29e9092e0d0dd304ec113dcc92e171f4 (patch)
treefff1e24c94b44f8fbaa2fff3f9b676ca337b6d21 /src
parentbf35a9ab1e9664846c9e03c9ffa5eba589bed159 (diff)
downloadgem5-30488f4a29e9092e0d0dd304ec113dcc92e171f4.tar.xz
add a trackBranch option
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/O3CPU.py1
-rw-r--r--src/cpu/o3/lsq_unit.hh1
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh9
3 files changed, 7 insertions, 4 deletions
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 1a97faced..11a2133e6 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -170,6 +170,7 @@ class DerivO3CPU(BaseCPU):
needsTSO = Param.Bool(False, "Enable TSO Memory model")
allowSpecBuffHit = Param.Bool(True, "Enable hit/reuse spec buffer entries")
useIFT = Param.Bool(False, "use IFT to filter")
+ trackBranch = Param.Bool(True, "Track tainted branches")
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index c512ef819..fbe5248f7 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -529,6 +529,7 @@ class LSQUnit {
bool isFuturistic;
bool allowSpecBuffHit;
bool useIFT;
+ bool trackBranch;
/* [mengjia] different schemes determine values of 4 variables. */
// Will also need how many read/write ports the Dcache has. Or keep track
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f22383506..9d71c2093 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -232,9 +232,10 @@ LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
needsTSO = params->needsTSO;
allowSpecBuffHit = params->allowSpecBuffHit;
useIFT = params->useIFT;
+ trackBranch = params->trackBranch;
cprintf("Info: simulation uses scheme: %s; "
- "needsTSO=%d; allowSpecBuffHit=%d; useIFT=%d\n",
- scheme, needsTSO, allowSpecBuffHit, useIFT);
+ "needsTSO=%d; allowSpecBuffHit=%d; useIFT=%d; trackBranch=%d\n",
+ scheme, needsTSO, allowSpecBuffHit, useIFT, trackBranch);
// [mengjia] end of setting configuration variables
resetState();
@@ -1033,7 +1034,7 @@ LSQUnit<Impl>::updateVisibleState()
/* set taint for dst registers */
inst->taintDestRegs(true, "unsafe load");
bool doSpecLoad = false;
- if (inst->afterTaintedBranch) {
+ if (trackBranch && inst->afterTaintedBranch) {
doSpecLoad = true;
DPRINTF(LSQUnit, "load inst [sn:%lli] %s is after a tainted branch.\n", inst->seqNum, inst->pcState());
} else if (inst->srcTainted()) {
@@ -1083,7 +1084,7 @@ LSQUnit<Impl>::updateVisibleState()
if (inst->needPostFetch()) {
doSpecLoad = true;
DPRINTF(LSQUnit, "load inst [sn:%lli] %s needs post fetch.\n", inst->seqNum, inst->pcState());
- } else if (inst->afterTaintedBranch) {
+ } else if (trackBranch && inst->afterTaintedBranch) {
doSpecLoad = true;
DPRINTF(LSQUnit, "load inst [sn:%lli] %s is after a tainted branch.\n", inst->seqNum, inst->pcState());
} else if (inst->srcTainted()) {