summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-06-27 05:49:49 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-06-27 05:49:49 -0400
commit368f50a0a1caaddf84ef35a5597f5eee75495cbb (patch)
treeffc012847a23ee2e49c2c45313ec4d4f4cc3ead3 /src
parent718fb407098ed8751a71eda7f2ce9b24ccd1d24b (diff)
downloadgem5-368f50a0a1caaddf84ef35a5597f5eee75495cbb.tar.xz
mem: Cycles converted to Ticks in atomic cache accesses
This patch fixes an outstanding issue in the cache timing calculations where an atomic access returned a time in Cycles, but the port forwarded it on as if it was in Ticks. A separate patch will update the regression stats.
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/cache.hh10
-rw-r--r--src/mem/cache/cache_impl.hh16
2 files changed, 11 insertions, 15 deletions
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index d27dfc5e2..de98398d6 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -263,17 +263,17 @@ class Cache : public BaseCache
/**
* Performs the access specified by the request.
* @param pkt The request to perform.
- * @return The number of cycles required for the access.
+ * @return The number of ticks required for the access.
*/
- Cycles recvAtomic(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt);
/**
* Snoop for the provided request in the cache and return the estimated
- * time of completion.
+ * time taken.
* @param pkt The memory request to snoop
- * @return The number of cycles required for the snoop.
+ * @return The number of ticks required for the snoop.
*/
- Cycles recvAtomicSnoop(PacketPtr pkt);
+ Tick recvAtomicSnoop(PacketPtr pkt);
/**
* Performs the access specified by the request.
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 60b72b521..f697f84e4 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -644,7 +644,7 @@ Cache<TagStore>::getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
template<class TagStore>
-Cycles
+Tick
Cache<TagStore>::recvAtomic(PacketPtr pkt)
{
Cycles lat = hitLatency;
@@ -678,7 +678,7 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt)
pkt->cmdString(), pkt->getAddr());
}
- return lat;
+ return lat * clockPeriod();
}
// should assert here that there are no outstanding MSHRs or
@@ -763,7 +763,7 @@ Cache<TagStore>::recvAtomic(PacketPtr pkt)
pkt->makeAtomicResponse();
}
- return lat;
+ return lat * clockPeriod();
}
@@ -1510,7 +1510,7 @@ Cache<TagStore>::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
}
template<class TagStore>
-Cycles
+Tick
Cache<TagStore>::recvAtomicSnoop(PacketPtr pkt)
{
// Snoops shouldn't happen when bypassing caches
@@ -1519,12 +1519,12 @@ Cache<TagStore>::recvAtomicSnoop(PacketPtr pkt)
if (pkt->req->isUncacheable() || pkt->cmd == MemCmd::Writeback) {
// Can't get a hit on an uncacheable address
// Revisit this for multi level coherence
- return hitLatency;
+ return 0;
}
BlkType *blk = tags->findBlock(pkt->getAddr());
handleSnoop(pkt, blk, false, false, false);
- return hitLatency;
+ return hitLatency * clockPeriod();
}
@@ -1777,8 +1777,6 @@ template<class TagStore>
Tick
Cache<TagStore>::CpuSidePort::recvAtomic(PacketPtr pkt)
{
- // @todo: Note that this is currently using cycles instead of
- // ticks and will be fixed in a future patch
return cache->recvAtomic(pkt);
}
@@ -1825,8 +1823,6 @@ template<class TagStore>
Tick
Cache<TagStore>::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
{
- // @todo: Note that this is using cycles and not ticks and will be
- // fixed in a future patch
return cache->recvAtomicSnoop(pkt);
}