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authorLisa Hsu <hsul@eecs.umich.edu>2008-10-23 16:49:17 -0400
committerLisa Hsu <hsul@eecs.umich.edu>2008-10-23 16:49:17 -0400
commit8788d703f81cef20916ffd2c7e0d28031cf65df8 (patch)
tree48795566574ac52ef9183f8ada9b60874df2bc04 /src
parent546a6c0c1b6dfc23bac1f74c6adec413931c6608 (diff)
downloadgem5-8788d703f81cef20916ffd2c7e0d28031cf65df8.tar.xz
s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
comments.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/cpu.cc2
-rw-r--r--src/cpu/o3/cpu.hh6
-rw-r--r--src/mem/cache/cache.hh5
3 files changed, 6 insertions, 7 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 04f344930..1b7a3a17c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -62,7 +62,7 @@ class BaseCPUParams;
using namespace TheISA;
BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
- : BaseCPU(params), cpu_id(0)
+ : BaseCPU(params), cpuId(0)
{
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 8cfc9affa..d1cc8bea5 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -76,13 +76,13 @@ class BaseO3CPU : public BaseCPU
void regStats();
/** Sets this CPU's ID. */
- void setCpuId(int id) { cpu_id = id; }
+ void setCpuId(int id) { cpuId = id; }
/** Reads this CPU's ID. */
- int readCpuId() { return cpu_id; }
+ int readCpuId() { return cpuId; }
protected:
- int cpu_id;
+ int cpuId;
};
/**
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 510e67ba6..4db5230f8 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -137,7 +137,7 @@ class Cache : public BaseCache
BlkType *tempBlock;
/**
- * Can this cache should allocate a block on a line-sized write miss.
+ * This cache should allocate a block on a line-sized write miss.
*/
const bool doFastWrites;
@@ -149,8 +149,7 @@ class Cache : public BaseCache
* @param lat The latency of the access.
* @param writebacks List for any writebacks that need to be performed.
* @param update True if the replacement data should be updated.
- * @return Pointer to the cache block touched by the request. NULL if it
- * was a miss.
+ * @return Boolean indicating whether the request was satisfied.
*/
bool access(PacketPtr pkt, BlkType *&blk,
int &lat, PacketList &writebacks);