Merged with Gabe's recent changes.

24 files changed, 340 insertions, 683 deletions

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 4b5678e81..c03a99970 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -73,6 +73,7 @@ output exec {{
 
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/regredir.hh"
+#include "arch/generic/memhelpers.hh"
 #include "base/cp_annotate.hh"
 #include "base/fenv.hh"
 #include "config/ss_compatible_fp.hh"
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index fe72e049e..ed5128204 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -197,7 +197,7 @@ def template LoadExecute {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
@@ -223,7 +223,7 @@ def template LoadInitiateAcc {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
         }
 
         return fault;
@@ -241,7 +241,7 @@ def template LoadCompleteAcc {{
         %(fp_enable_check)s;
         %(op_decl)s;
 
-        Mem = pkt->get<typeof(Mem)>();
+        getMem(pkt, Mem, traceData);
 
         if (fault == NoFault) {
             %(memacc_code)s;
@@ -273,8 +273,8 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA,
+                    memAccessFlags, NULL);
         }
 
         if (fault == NoFault) {
@@ -307,8 +307,8 @@ def template StoreCondExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
+            fault = writeMemAtomic(xc, traceData, Mem, EA,
+                    memAccessFlags, &write_result);
         }
 
         if (fault == NoFault) {
@@ -340,8 +340,8 @@ def template StoreInitiateAcc {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemTiming(xc, traceData, Mem, EA,
+                    memAccessFlags, NULL);
         }
 
         return fault;
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index b54545e10..bfd6fedd4 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -80,6 +80,7 @@ output exec {{
 #include "arch/arm/faults.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
+#include "arch/generic/memhelpers.hh"
 #include "base/condcodes.hh"
 #include "sim/pseudo_inst.hh"
 #if defined(linux)
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index cb255feda..a00114409 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -87,8 +87,8 @@ def template SwapExecute {{
             %(preacc_code)s;
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem,
-                        EA, memAccessFlags, &memData);
+                fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                        &memData);
             }
 
             if (fault == NoFault) {
@@ -123,8 +123,8 @@ def template SwapInitiateAcc {{
             %(preacc_code)s;
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, &memData);
+                fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                        &memData);
             }
         } else {
             xc->setPredicate(false);
@@ -147,7 +147,8 @@ def template SwapCompleteAcc {{
         if (%(predicate_test)s)
         {
             // ARM instructions will not have a pkt if the predicate is false
-            uint64_t memData = pkt->get<typeof(Mem)>();
+            getMem(pkt, Mem, traceData);
+            uint64_t memData = Mem;
 
             %(postacc_code)s;
 
@@ -174,7 +175,7 @@ def template LoadExecute {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+                fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
                 %(memacc_code)s;
             }
 
@@ -208,7 +209,7 @@ def template NeonLoadExecute {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+                fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
                 %(memacc_code)s;
             }
 
@@ -241,8 +242,8 @@ def template StoreExecute {{
             }
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, NULL);
+                fault = writeMemAtomic(xc, traceData, Mem, EA,
+                        memAccessFlags, NULL);
             }
 
             if (fault == NoFault) {
@@ -279,8 +280,8 @@ def template NeonStoreExecute {{
             }
 
             if (fault == NoFault) {
-                fault = xc->writeBytes(dataPtr, %(size)d, EA,
-                                       memAccessFlags, NULL);
+                fault = xc->writeMem(dataPtr, %(size)d, EA,
+                                     memAccessFlags, NULL);
             }
 
             if (fault == NoFault) {
@@ -314,8 +315,8 @@ def template StoreExExecute {{
             uint64_t writeResult;
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, &writeResult);
+                fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                        &writeResult);
             }
 
             if (fault == NoFault) {
@@ -351,8 +352,8 @@ def template StoreExInitiateAcc {{
             }
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, NULL);
+                fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                        NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -380,8 +381,8 @@ def template StoreInitiateAcc {{
             }
 
             if (fault == NoFault) {
-                fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                                  memAccessFlags, NULL);
+                fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                        NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -412,8 +413,8 @@ def template NeonStoreInitiateAcc {{
             }
 
             if (fault == NoFault) {
-                fault = xc->writeBytes(memUnion.bytes, %(size)d, EA,
-                                       memAccessFlags, NULL);
+                fault = xc->writeMem(memUnion.bytes, %(size)d, EA,
+                                     memAccessFlags, NULL);
             }
         } else {
             xc->setPredicate(false);
@@ -437,7 +438,7 @@ def template LoadInitiateAcc {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+                fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
             }
         } else {
             xc->setPredicate(false);
@@ -466,7 +467,7 @@ def template NeonLoadInitiateAcc {{
         if (%(predicate_test)s)
         {
             if (fault == NoFault) {
-                fault = xc->readBytes(EA, dataPtr, %(size)d, memAccessFlags);
+                fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags);
             }
         } else {
             xc->setPredicate(false);
@@ -489,7 +490,7 @@ def template LoadCompleteAcc {{
         if (%(predicate_test)s)
         {
             // ARM instructions will not have a pkt if the predicate is false
-            Mem = pkt->get<typeof(Mem)>();
+            getMem(pkt, Mem, traceData);
 
             if (fault == NoFault) {
                 %(memacc_code)s;
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
new file mode 100644
index 000000000..c753aaf2a
--- /dev/null
+++ b/src/arch/generic/memhelpers.hh
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_GENERIC_MEMHELPERS_HH__
+#define __ARCH_GENERIC_MEMHELPERS_HH__
+
+#include "base/types.hh"
+#include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/insttracer.hh"
+
+/// Read from memory in timing mode.
+template <class XC, class MemT>
+Fault
+readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
+        MemT &mem, unsigned flags)
+{
+    return xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
+}
+
+/// Extract the data returned from a timing mode read.
+template <class MemT>
+void
+getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+{
+    mem = pkt->get<MemT>();
+    if (traceData)
+        traceData->setData(mem);
+}
+
+/// Read from memory in atomic mode.
+template <class XC, class MemT>
+Fault
+readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+        unsigned flags)
+{
+    memset(&mem, 0, sizeof(mem));
+    Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
+    if (fault == NoFault) {
+        mem = gtoh(mem);
+        if (traceData)
+            traceData->setData(mem);
+    }
+    return fault;
+}
+
+/// Write to memory in timing mode.
+template <class XC, class MemT>
+Fault
+writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+        unsigned flags, uint64_t *res)
+{
+    if (traceData) {
+        traceData->setData(mem);
+    }
+    mem = TheISA::htog(mem);
+    return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
+}
+
+/// Write to memory in atomic mode.
+template <class XC, class MemT>
+Fault
+writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+        Addr addr, unsigned flags, uint64_t *res)
+{
+    Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
+    if (fault == NoFault && res != NULL) {
+        *res = gtoh((MemT)*res);
+    }
+    return fault;
+}
+
+#endif
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index c4666e4ab..bc3a2b3ce 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -216,7 +216,7 @@ def template LoadExecute {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
@@ -248,7 +248,7 @@ def template LoadInitiateAcc {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
         }
 
         return fault;
@@ -272,7 +272,7 @@ def template LoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        Mem = pkt->get<typeof(Mem)>();
+        getMem(pkt, Mem, traceData);
 
         if (fault == NoFault) {
             %(memacc_code)s;
@@ -303,8 +303,8 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         if (fault == NoFault) {
@@ -339,8 +339,8 @@ def template StoreFPExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         if (fault == NoFault) {
@@ -373,8 +373,8 @@ def template StoreCondExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    &write_result);
         }
 
         if (fault == NoFault) {
@@ -406,8 +406,8 @@ def template StoreInitiateAcc {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         return fault;
@@ -559,14 +559,15 @@ def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
 
 def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
                      mem_flags = [], inst_flags = []) {{
-    decl_code = 'uint32_t mem_word = 0;\n'
-    decl_code += 'uint32_t unaligned_addr = Rs + disp;\n'
-    decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n'
-    decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n'
-    decl_code += '\tbyte_offset ^= 3;\n'
-    decl_code += '#endif\n'
-    decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
-    #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
+    decl_code = '''
+        uint32_t mem_word = 0;
+        uint32_t unaligned_addr = Rs + disp;
+        uint32_t byte_offset = unaligned_addr & 3;
+        #if BYTE_ORDER == BIG_ENDIAN
+            byte_offset ^= 3;
+        #endif
+        fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
+    '''
     memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
 
     (header_output, decoder_output, decode_block, exec_output) = \
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index 73d751f6e..9c1183839 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -68,6 +68,7 @@ using namespace MipsISA;
 output exec {{
 #include <math.h>
 
+#include "arch/generic/memhelpers.hh"
 #include "arch/mips/dsp.hh"
 #include "arch/mips/dt_constants.hh"
 #include "arch/mips/faults.hh"
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 014e4ff5a..519275a16 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -84,7 +84,7 @@ def template LoadExecute {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
+            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
@@ -109,7 +109,7 @@ def template LoadInitiateAcc {{
         %(ea_code)s;
 
         if (fault == NoFault) {
-            fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
+            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
             xc->setEA(EA);
         }
 
@@ -132,7 +132,7 @@ def template LoadCompleteAcc {{
 
         EA = xc->getEA();
 
-        val = pkt->get<uint%(mem_acc_size)d_t>();
+        getMem(pkt, val, traceData);
         *((uint%(mem_acc_size)d_t*)&Mem) = val;
 
         if (fault == NoFault) {
@@ -164,8 +164,8 @@ def template StoreExecute {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         if (fault == NoFault) {
@@ -193,8 +193,8 @@ def template StoreInitiateAcc {{
         }
 
         if (fault == NoFault) {
-            fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, NULL);
+            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
+                    NULL);
         }
 
         // Need to write back any potential address register update
diff --git a/src/arch/power/isa/includes.isa b/src/arch/power/isa/includes.isa
index 5c2b74141..f6292eaab 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -75,6 +75,7 @@ output exec {{
 #include <fenv.h>
 #endif
 
+#include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
 #include "arch/power/isa_traits.hh"
 #include "arch/power/utility.hh"
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 99bbf3a68..17a490c4b 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -50,8 +50,8 @@ def template SwapExecute {{
             }
             if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((uint%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, &mem_data);
+                fault = writeMemAtomic(xc, traceData, Mem, EA,
+                        %(asi_val)s, &mem_data);
             }
             if (fault == NoFault) {
                 // Handle the swapping
@@ -87,8 +87,8 @@ def template SwapInitiateAcc {{
             }
             if (fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((uint%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, &mem_data);
+                fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s,
+                        &mem_data);
             }
             return fault;
         }
@@ -103,7 +103,8 @@ def template SwapCompleteAcc {{
             Fault fault = NoFault;
             %(op_decl)s;
 
-            uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>();
+            getMem(pkt, Mem, traceData);
+            uint64_t mem_data = Mem;
 
             if (fault == NoFault) {
                 // Handle the swapping
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index aaa04b4bf..06206c02b 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -143,7 +143,7 @@ def template LoadExecute {{
             %(fault_check)s;
             if (fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
+                fault = readMemAtomic(xc, traceData, EA, Mem, %(asi_val)s);
             }
             if (fault == NoFault) {
                 %(code)s;
@@ -171,7 +171,7 @@ def template LoadInitiateAcc {{
             %(fault_check)s;
             if (fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s);
+                fault = readMemTiming(xc, traceData, EA, Mem, %(asi_val)s);
             }
             return fault;
         }
@@ -184,7 +184,7 @@ def template LoadCompleteAcc {{
             Fault fault = NoFault;
             %(op_decl)s;
             %(op_rd)s;
-            Mem = pkt->get<typeof(Mem)>();
+            getMem(pkt, Mem, traceData);
             %(code)s;
             if (fault == NoFault) {
                 %(op_wb)s;
@@ -214,8 +214,7 @@ def template StoreExecute {{
             }
             if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, 0);
+                fault = writeMemAtomic(xc, traceData, Mem, EA, %(asi_val)s, 0);
             }
             if (fault == NoFault) {
                 // Write the resulting state to the execution context
@@ -245,8 +244,7 @@ def template StoreInitiateAcc {{
             }
             if (storeCond && fault == NoFault) {
                 %(EA_trunc)s
-                fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem,
-                        EA, %(asi_val)s, 0);
+                fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s, 0);
             }
             return fault;
         }
diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa
index 885cd9cc2..db3677752 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -70,6 +70,7 @@ output exec {{
 #include <cmath>
 #include <limits>
 
+#include "arch/generic/memhelpers.hh"
 #include "arch/sparc/asi.hh"
 #include "base/bigint.hh"
 #include "cpu/base.hh"
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index 5487655e2..c618bc128 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -97,73 +97,6 @@ namespace X86ISA
 
         std::string generateDisassembly(Addr pc,
             const SymbolTable *symtab) const;
-
-        template<class Context, class MemType>
-        Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const
-        {
-            Fault fault = NoFault;
-            switch(dataSize)
-            {
-              case 1:
-                fault = xc->read(EA, (uint8_t&)Mem, flags);
-                break;
-              case 2:
-                fault = xc->read(EA, (uint16_t&)Mem, flags);
-                break;
-              case 4:
-                fault = xc->read(EA, (uint32_t&)Mem, flags);
-                break;
-              case 8:
-                fault = xc->read(EA, (uint64_t&)Mem, flags);
-                break;
-              default:
-                panic("Bad operand size %d for read at %#x.\n", dataSize, EA);
-            }
-            return fault;
-        }
-
-        template<class Context, class MemType>
-        Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const
-        {
-            Fault fault = NoFault;
-            switch(dataSize)
-            {
-              case 1:
-                fault = xc->write((uint8_t&)Mem, EA, flags, 0);
-                break;
-              case 2:
-                fault = xc->write((uint16_t&)Mem, EA, flags, 0);
-                break;
-              case 4:
-                fault = xc->write((uint32_t&)Mem, EA, flags, 0);
-                break;
-              case 8:
-                fault = xc->write((uint64_t&)Mem, EA, flags, 0);
-                break;
-              default:
-                panic("Bad operand size %d for write at %#x.\n", dataSize, EA);
-            }
-            return fault;
-        }
-
-        uint64_t
-        get(PacketPtr pkt) const
-        {
-            switch(dataSize)
-            {
-              case 1:
-                return pkt->get<uint8_t>();
-              case 2:
-                return pkt->get<uint16_t>();
-              case 4:
-                return pkt->get<uint32_t>();
-              case 8:
-                return pkt->get<uint64_t>();
-              default:
-                panic("Bad operand size %d for read at %#x.\n",
-                        dataSize, pkt->getAddr());
-            }
-        }
     };
 }
 
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 8d4af6829..dc8abbc66 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -112,6 +112,7 @@ output exec {{
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/cpuid.hh"
 #include "arch/x86/faults.hh"
+#include "arch/x86/memhelpers.hh"
 #include "arch/x86/tlb.hh"
 #include "base/bigint.hh"
 #include "base/compiler.hh"
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 811b35c8a..c88161f34 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -98,7 +98,7 @@ def template MicroLoadExecute {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        fault = read(xc, EA, Mem, memFlags);
+        fault = readMemAtomic(xc, traceData, EA, Mem, dataSize, memFlags);
 
         if (fault == NoFault) {
             %(code)s;
@@ -127,7 +127,7 @@ def template MicroLoadInitiateAcc {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        fault = read(xc, EA, Mem, memFlags);
+        fault = readMemTiming(xc, traceData, EA, Mem, dataSize, memFlags);
 
         return fault;
     }
@@ -143,7 +143,7 @@ def template MicroLoadCompleteAcc {{
         %(op_decl)s;
         %(op_rd)s;
 
-        Mem = get(pkt);
+        Mem = getMem(pkt, dataSize, traceData);
 
         %(code)s;
 
@@ -174,7 +174,8 @@ def template MicroStoreExecute {{
 
         if(fault == NoFault)
         {
-            fault = write(xc, Mem, EA, memFlags);
+            fault = writeMemAtomic(xc, traceData, Mem, dataSize, EA,
+                    memFlags, NULL);
             if(fault == NoFault)
             {
                 %(op_wb)s;
@@ -201,7 +202,8 @@ def template MicroStoreInitiateAcc {{
 
         if(fault == NoFault)
         {
-            write(xc, Mem, EA, memFlags);
+            fault = writeMemTiming(xc, traceData, Mem, dataSize, EA,
+                    memFlags, NULL);
         }
         return fault;
     }
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
new file mode 100644
index 000000000..43612c9be
--- /dev/null
+++ b/src/arch/x86/memhelpers.hh
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_MEMHELPERS_HH__
+#define __ARCH_X86_MEMHELPERS_HH__
+
+#include "base/types.hh"
+#include "sim/byteswap.hh"
+#include "sim/fault_fwd.hh"
+#include "sim/insttracer.hh"
+
+namespace X86ISA
+{
+
+template <class XC>
+Fault
+readMemTiming(XC *xc, Trace::InstRecord *traceData, Addr addr,
+        uint64_t &mem, unsigned dataSize, unsigned flags)
+{
+    return xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
+}
+
+static inline uint64_t
+getMem(PacketPtr pkt, unsigned dataSize, Trace::InstRecord *traceData)
+{
+    uint64_t mem;
+    switch (dataSize) {
+      case 1:
+        mem = pkt->get<uint8_t>();
+        break;
+      case 2:
+        mem = pkt->get<uint16_t>();
+        break;
+      case 4:
+        mem = pkt->get<uint32_t>();
+        break;
+      case 8:
+        mem = pkt->get<uint64_t>();
+        break;
+      default:
+        panic("Unhandled size in getMem.\n");
+    }
+    if (traceData)
+        traceData->setData(mem);
+    return mem;
+}
+
+template <class XC>
+Fault
+readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
+        unsigned dataSize, unsigned flags)
+{
+    memset(&mem, 0, sizeof(mem));
+    Fault fault = readMemTiming(xc, traceData, addr, mem, dataSize, flags);
+    if (fault == NoFault) {
+        // If LE to LE, this is a nop, if LE to BE, the actual data ends up
+        // in the right place because the LSBs where at the low addresses on
+        // access. This doesn't work for BE guests.
+        mem = gtoh(mem);
+        if (traceData)
+            traceData->setData(mem);
+    }
+    return fault;
+}
+
+template <class XC>
+Fault
+writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
+        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+{
+    if (traceData) {
+        traceData->setData(mem);
+    }
+    mem = TheISA::htog(mem);
+    return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
+}
+
+template <class XC>
+Fault
+writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
+        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
+{
+    Fault fault = writeMemTiming(xc, traceData, mem, dataSize, addr, flags,
+            res);
+    if (fault == NoFault && res != NULL) {
+        *res = gtoh(*res);
+    }
+    return fault;
+}
+
+}
+
+#endif
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4c7abe376..f0d36cc83 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -124,31 +124,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
         cpu->demapPage(vaddr, asn);
     }
 
-    /**
-     * Does a read to a given address.
-     * @param addr The address to read.
-     * @param data The read's data is written into this parameter.
-     * @param flags The request's flags.
-     * @return Returns any fault due to the read.
-     */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
-
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /**
-     * Does a write to a given address.
-     * @param data The data to be written.
-     * @param addr The address to write to.
-     * @param flags The request's flags.
-     * @param res The result of the write (for load locked/store conditionals).
-     * @return Returns any fault due to the write.
-     */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Splits a request in two if it crosses a dcache block. */
     void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@@ -862,8 +841,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
 template<class Impl>
 Fault
-BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
-                             unsigned size, unsigned flags)
+BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
+                           unsigned size, unsigned flags)
 {
     reqMade = true;
     Request *req = NULL;
@@ -913,25 +892,9 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
 }
 
 template<class Impl>
-template<class T>
-inline Fault
-BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
-{
-    Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-
-    data = TheISA::gtoh(data);
-
-    if (traceData) {
-        traceData->setData(data);
-    }
-
-    return fault;
-}
-
-template<class Impl>
 Fault
-BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
-                              Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
+                            Addr addr, unsigned flags, uint64_t *res)
 {
     if (traceData) {
         traceData->setAddr(addr);
@@ -968,18 +931,6 @@ BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
 }
 
 template<class Impl>
-template<class T>
-inline Fault
-BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    if (traceData) {
-        traceData->setData(data);
-    }
-    data = TheISA::htog(data);
-    return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
-}
-
-template<class Impl>
 inline void
 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
                                 RequestPtr &sreqHigh)
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index a8704851f..61c9b24a9 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -106,21 +106,10 @@ class ExecContext {
     /** Returns a pointer to the ThreadContext. */
     ThreadContext *tcBase();
 
-    /** Reads an address, creating a memory request with the given
-     * flags.  Stores result of read in data. */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /** Writes to an address, creating a memory request with the given
-     * flags.  Writes data to memory.  For store conditionals, returns
-     * the result of the store in res. */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
 #if FULL_SYSTEM
     /** Somewhat Alpha-specific function that handles returning from
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index a90c2cdb4..5343206c1 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -559,155 +559,19 @@ InOrderDynInst::deallocateContext(int thread_num)
 }
 
 Fault
-InOrderDynInst::readBytes(Addr addr, uint8_t *data,
-                          unsigned size, unsigned flags)
+InOrderDynInst::readMem(Addr addr, uint8_t *data,
+                        unsigned size, unsigned flags)
 {
     return cpu->read(this, addr, data, size, flags);
 }
 
-template<class T>
-inline Fault
-InOrderDynInst::read(Addr addr, T &data, unsigned flags)
-{
-    if (traceData) {
-        traceData->setAddr(addr);
-        traceData->setData(data);
-    }
-    Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-    //@todo: the below lines should be unnecessary, timing access
-    // wont have valid data right here
-    DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
-    data = TheISA::gtoh(data);
-    DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
-
-    if (traceData)
-        traceData->setData(data);
-    return fault;
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, double &data, unsigned flags)
-{
-    return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, float &data, unsigned flags)
-{
-    return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
-{
-    return read(addr, (uint32_t&)data, flags);
-}
-
 Fault
-InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
-                           Addr addr, unsigned flags, uint64_t *res)
+InOrderDynInst::writeMem(uint8_t *data, unsigned size,
+                         Addr addr, unsigned flags, uint64_t *res)
 {
     return cpu->write(this, data, size, addr, flags, res);
 }
 
-template<class T>
-inline Fault
-InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    if (traceData) {
-        traceData->setAddr(addr);
-        traceData->setData(data);
-    }
-    data = TheISA::htog(data);
-    return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-InOrderDynInst::write(Twin32_t data, Addr addr,
-                      unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(Twin64_t data, Addr addr,
-                      unsigned flags, uint64_t *res);
-template
-Fault
-InOrderDynInst::write(uint64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint16_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint8_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write((uint32_t)data, addr, flags, res);
-}
-
 
 void
 InOrderDynInst::dump()
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 205bb0f82..ecaf23aab 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -612,32 +612,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     // MEMORY ACCESS
     //
     ////////////////////////////////////////////
-    /**
-     * Does a read to a given address.
-     * @param addr The address to read.
-     * @param data The read's data is written into this parameter.
-     * @param flags The request's flags.
-     * @return Returns any fault due to the read.
-     */
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
-
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    /**
-     * Does a write to a given address.
-     * @param data The data to be written.
-     * @param addr The address to write to.
-     * @param flags The request's flags.
-     * @param res The result of the write (for load locked/store conditionals).
-     * @return Returns any fault due to the write.
-     */
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags,
-                        uint64_t *res);
 
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
      *  Access Only valid for memory operations.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index f3d79dd2b..5376519d4 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -299,8 +299,8 @@ AtomicSimpleCPU::suspendContext(int thread_num)
 
 
 Fault
-AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
-                           unsigned size, unsigned flags)
+AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
+                         unsigned size, unsigned flags)
 {
     // use the CPU's statically allocated read request and packet objects
     Request *req = &data_read_req;
@@ -386,75 +386,9 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
 }
 
 
-template <class T>
 Fault
-AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
-    uint8_t *dataPtr = (uint8_t *)&data;
-    memset(dataPtr, 0, sizeof(data));
-    Fault fault = readBytes(addr, dataPtr, sizeof(data), flags);
-    if (fault == NoFault) {
-        data = gtoh(data);
-        if (traceData)
-            traceData->setData(data);
-    }
-    return fault;
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
-    return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
-    return read(addr, *(uint32_t*)&data, flags);
-}
-
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
-    return read(addr, (uint32_t&)data, flags);
-}
-
-
-Fault
-AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
-                            Addr addr, unsigned flags, uint64_t *res)
+AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
+                          Addr addr, unsigned flags, uint64_t *res)
 {
     // use the CPU's statically allocated write request and packet objects
     Request *req = &data_write_req;
@@ -555,80 +489,6 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
 }
 
 
-template <class T>
-Fault
-AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    uint8_t *dataPtr = (uint8_t *)&data;
-    if (traceData)
-        traceData->setData(data);
-    data = htog(data);
-
-    Fault fault = writeBytes(dataPtr, sizeof(data), addr, flags, res);
-    if (fault == NoFault && data_write_req.isSwap()) {
-        *res = gtoh((T)*res);
-    }
-    return fault;
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-AtomicSimpleCPU::write(Twin32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(Twin64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint16_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint8_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write((uint32_t)data, addr, flags, res);
-}
-
-
 void
 AtomicSimpleCPU::tick()
 {
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 5ec1970e7..246afa0b2 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -131,16 +131,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     /**
      * Print state of address in memory system via PrintReq (for
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 187b38b85..1c726ba57 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -432,8 +432,8 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 }
 
 Fault
-TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
-                           unsigned size, unsigned flags)
+TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
+                         unsigned size, unsigned flags)
 {
     Fault fault;
     const int asid = 0;
@@ -479,62 +479,6 @@ TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
     return NoFault;
 }
 
-template <class T>
-Fault
-TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
-    return readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
-    return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
-    return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
-    return read(addr, (uint32_t&)data, flags);
-}
-
 bool
 TimingSimpleCPU::handleWritePacket()
 {
@@ -556,9 +500,12 @@ TimingSimpleCPU::handleWritePacket()
 }
 
 Fault
-TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
-                                 Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
+                          Addr addr, unsigned flags, uint64_t *res)
 {
+    uint8_t *newData = new uint8_t[size];
+    memcpy(newData, data, size);
+
     const int asid = 0;
     const ThreadID tid = 0;
     const Addr pc = thread->instAddr();
@@ -582,7 +529,7 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
         req->splitOnVaddr(split_addr, req1, req2);
 
         WholeTranslationState *state =
-            new WholeTranslationState(req, req1, req2, data, res, mode);
+            new WholeTranslationState(req, req1, req2, newData, res, mode);
         DataTranslation<TimingSimpleCPU> *trans1 =
             new DataTranslation<TimingSimpleCPU>(this, state, 0);
         DataTranslation<TimingSimpleCPU> *trans2 =
@@ -592,7 +539,7 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
         thread->dtb->translateTiming(req2, tc, trans2, mode);
     } else {
         WholeTranslationState *state =
-            new WholeTranslationState(req, data, res, mode);
+            new WholeTranslationState(req, newData, res, mode);
         DataTranslation<TimingSimpleCPU> *translation =
             new DataTranslation<TimingSimpleCPU>(this, state);
         thread->dtb->translateTiming(req, tc, translation, mode);
@@ -602,84 +549,6 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
     return NoFault;
 }
 
-Fault
-TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
-                            Addr addr, unsigned flags, uint64_t *res)
-{
-    uint8_t *newData = new uint8_t[size];
-    memcpy(newData, data, size);
-    return writeTheseBytes(newData, size, addr, flags, res);
-}
-
-template <class T>
-Fault
-TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
-    if (traceData) {
-        traceData->setData(data);
-    }
-    T *dataP = (T*) new uint8_t[sizeof(T)];
-    *dataP = TheISA::htog(data);
-
-    return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template
-Fault
-TimingSimpleCPU::write(Twin32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(Twin64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint64_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint32_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint16_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint8_t data, Addr addr,
-                       unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
-    return write((uint32_t)data, addr, flags, res);
-}
-
 
 void
 TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 778506703..4301dfca7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -256,16 +256,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
     virtual void activateContext(int thread_num, int delay);
     virtual void suspendContext(int thread_num);
 
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
+    Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 
-    Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    Fault writeBytes(uint8_t *data, unsigned size,
-                     Addr addr, unsigned flags, uint64_t *res);
+    Fault writeMem(uint8_t *data, unsigned size,
+                   Addr addr, unsigned flags, uint64_t *res);
 
     void fetch();
     void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
@@ -287,11 +281,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
   private:
 
-    // The backend for writeBytes and write. It's the same as writeBytes, but
-    // doesn't make a copy of data.
-    Fault writeTheseBytes(uint8_t *data, unsigned size,
-                          Addr addr, unsigned flags, uint64_t *res);
-
     typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
     FetchEvent fetchEvent;