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authorGabe Black <gblack@eecs.umich.edu>2006-12-18 18:17:30 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-12-18 18:17:30 -0500
commitaf1e8d2d40183549da1b982ae6e994311a77fd6a (patch)
tree01cc2c8bf8b34c1a6a5367e8ef3ad45eacfa8f7f /src
parent9e7dc343832f473b2058d4f9b39a27430142006f (diff)
downloadgem5-af1e8d2d40183549da1b982ae6e994311a77fd6a.tar.xz
Fixing the extended twin format to go with the new isa parser interface.
--HG-- extra : convert_revision : f41183cfa011b21e7ab8cbcdef0ac1d464692362
Diffstat (limited to 'src')
-rw-r--r--src/arch/sparc/isa/formats/mem/blockmem.isa14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 25fffc02b..c4f052f98 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -494,18 +494,18 @@ let {{
else:
flag_code = "flags[IsDelayedCommit] = true;"
pcedCode = matcher.sub("RdLow", code)
- iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
- opt_flags, {"ea_code": addrCalcReg,
+ iop = InstObjParams(name, Name, 'TwinMem',
+ {"code": pcedCode, "ea_code": addrCalcReg,
"fault_check": faultCode, "micro_pc": microPc,
- "set_flags": flag_code})
- iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', pcedCode,
- opt_flags, {"ea_code": addrCalcImm,
+ "set_flags": flag_code}, opt_flags)
+ iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm',
+ {"code": pcedCode, "ea_code": addrCalcImm,
"fault_check": faultCode, "micro_pc": microPc,
- "set_flags": flag_code})
+ "set_flags": flag_code}, opt_flags)
decoder_output += BlockMemMicroConstructor.subst(iop)
decoder_output += BlockMemMicroConstructor.subst(iop_imm)
exec_output += doDualSplitExecute(
- pcedCode, addrCalcReg, addrCalcImm, LoadExecute, faultCode,
+ pcedCode, addrCalcReg, addrCalcImm, LoadFuncs, faultCode,
makeMicroName(name, microPc),
makeMicroName(name + "Imm", microPc),
makeMicroName(Name, microPc),