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authorGabe Black <gblack@eecs.umich.edu>2011-06-20 02:29:14 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-06-20 02:29:14 -0700
commitaffad299320e767b18c45a760c69a1ef287565bc (patch)
tree2e7a6e669e29b23e2a24f7c42b4814f8d605a9ef /src
parent97449ef3dad10f4846b5328c983cc8fe523b81f5 (diff)
downloadgem5-affad299320e767b18c45a760c69a1ef287565bc.tar.xz
InOder: Fix a compile error.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index f6f027850..73dd9c527 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -433,7 +433,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
if (inst->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
- "addr:%08p for [sn:%i].\n", tid, tlb_fault->name(),
+ "addr:%08p for [sn:%i].\n", tid, inst->fault->name(),
cache_req->memReq->getVaddr(), inst->seqNum);
tlbBlocked[tid] = true;