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authorIru Cai <mytbk920423@gmail.com>2019-04-17 10:14:47 +0800
committerIru Cai <mytbk920423@gmail.com>2019-04-17 10:14:47 +0800
commitbf35a9ab1e9664846c9e03c9ffa5eba589bed159 (patch)
treeeac672ba0b46b3d66992fb1ebb8789c97c608367 /src
parent5c5b6f718e0662e9226bcc55b96270082dffe91b (diff)
downloadgem5-bf35a9ab1e9664846c9e03c9ffa5eba589bed159.tar.xz
IFT for fence scheme
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh32
1 files changed, 26 insertions, 6 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index a45048ff9..f22383506 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1021,13 +1021,33 @@ LSQUnit<Impl>::updateVisibleState()
inst->seqNum, inst->pcState());
}
inst->fenceDelay(false);
- }else {
- if (!inst->fenceDelay()){
- DPRINTF(LSQUnit, "Deffering an inst [sn:%lli] PC %s"
- " due to virtual fence\n",
- inst->seqNum, inst->pcState());
+ } else {
+ if (!useIFT) {
+ if (!inst->fenceDelay()){
+ DPRINTF(LSQUnit, "Deffering an inst [sn:%lli] PC %s"
+ " due to virtual fence\n",
+ inst->seqNum, inst->pcState());
+ }
+ inst->fenceDelay(true);
+ } else {
+ /* set taint for dst registers */
+ inst->taintDestRegs(true, "unsafe load");
+ bool doSpecLoad = false;
+ if (inst->afterTaintedBranch) {
+ doSpecLoad = true;
+ DPRINTF(LSQUnit, "load inst [sn:%lli] %s is after a tainted branch.\n", inst->seqNum, inst->pcState());
+ } else if (inst->srcTainted()) {
+ doSpecLoad = true;
+ DPRINTF(LSQUnit, "source registers of load inst [sn:%lli] %s is tainted.\n", inst->seqNum, inst->pcState());
+ }
+ if (doSpecLoad) {
+ DPRINTF(LSQUnit, "load inst [sn:%lli] %s not safe, defer it.\n", inst->seqNum, inst->pcState());
+ inst->fenceDelay(true);
+ } else {
+ DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState());
+ inst->fenceDelay(false);
+ }
}
- inst->fenceDelay(true);
}
inst->readyToExpose(true);
} else if (loadInExec && isInvisibleSpec){