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authorKevin Lim <ktlim@umich.edu>2006-12-02 13:33:46 -0500
committerKevin Lim <ktlim@umich.edu>2006-12-02 13:33:46 -0500
commitc0f21b09c81e5562a916f7cb562a7df7f7709f4a (patch)
treea86574cd10c25266700ab644f6a025cacb9be994 /src
parentdc9438b1570c700d7261c7bf168953894624abf0 (diff)
downloadgem5-c0f21b09c81e5562a916f7cb562a7df7f7709f4a.tar.xz
Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay.
src/cpu/o3/commit_impl.hh: src/cpu/o3/fetch_impl.hh: Fixes for MIPS_SE compile. --HG-- extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/commit_impl.hh1
-rw-r--r--src/cpu/o3/fetch_impl.hh2
2 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e72679710..43305f962 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -748,6 +748,7 @@ DefaultCommit<Impl>::commit()
}
} else {
bdelay_done_seq_num = squashed_inst;
+ squash_bdelay_slot = true;
}
#endif
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 63d22b293..4c378e18b 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
ext_inst = TheISA::makeExtMI(inst, fetch_PC);
#elif THE_ISA == SPARC_ISA
ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#elif THE_ISA == MIPS_ISA
+ ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
#endif
// Create a new DynInst from the instruction fetched.