diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-11-02 13:11:38 -0500 |
---|---|---|
committer | Kevin Lim <ktlim@umich.edu> | 2006-11-02 13:11:38 -0500 |
commit | ccaf80cc46fb86639ab5ee166baca08277f5450f (patch) | |
tree | ca8ebf28f3092a5f5d06748b31a8dda66d106ee3 /src | |
parent | f763864786d7b95d46fba6f37e1e9ed601b60733 (diff) | |
download | gem5-ccaf80cc46fb86639ab5ee166baca08277f5450f.tar.xz |
Use ISA specific makeExtMI.
src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
--HG--
extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/alpha/utility.hh | 6 | ||||
-rw-r--r-- | src/cpu/checker/cpu_impl.hh | 5 | ||||
-rw-r--r-- | src/cpu/o3/fetch_impl.hh | 6 | ||||
-rw-r--r-- | src/cpu/ozone/front_end_impl.hh | 4 | ||||
-rw-r--r-- | src/cpu/simple/base.cc | 4 |
5 files changed, 21 insertions, 4 deletions
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh index 0304d1c3a..cb86c7e9e 100644 --- a/src/arch/alpha/utility.hh +++ b/src/arch/alpha/utility.hh @@ -43,11 +43,11 @@ namespace AlphaISA { static inline ExtMachInst - makeExtMI(MachInst inst, ThreadContext * xc) { + makeExtMI(MachInst inst, Addr pc) { #if FULL_SYSTEM ExtMachInst ext_inst = inst; - if (xc->readPC() && 0x1) - return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); + if (pc && 0x1) + return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); else return ext_inst; #else diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 36c7349e6..56e13dd1e 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -199,8 +199,13 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst) // Checks both the machine instruction and the PC. validateInst(inst); +#if THE_ISA == ALPHA_ISA + curStaticInst = StaticInst::decode(makeExtMI(machInst, + thread->readPC())); +#elif THE_ISA == SPARC_ISA curStaticInst = StaticInst::decode(makeExtMI(machInst, thread->getTC())); +#endif #if FULL_SYSTEM thread->setInst(machInst); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 2b152e376..31f3b96d6 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1117,7 +1117,11 @@ DefaultFetch<Impl>::fetch(bool &status_change) inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *> (&cacheData[tid][offset])); - ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid)); +#if THE_ISA == ALPHA_ISA + ext_inst = TheISA::makeExtMI(inst, fetch_PC); +#elif THE_ISA == SPARC_ISA + ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); +#endif // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 63cf0a952..6d02c58cb 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -882,7 +882,11 @@ FrontEnd<Impl>::getInstFromCacheline() // Get the instruction from the array of the cache line. inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset])); +#if THE_ISA == ALPHA_ISA + ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC); +#elif THE_ISA == SPARC_ISA ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc); +#endif // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst), diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 47b3b938f..6a2c0bbe9 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -398,7 +398,11 @@ BaseSimpleCPU::preExecute() inst = gtoh(inst); //If we're not in the middle of a macro instruction if (!curMacroStaticInst) { +#if THE_ISA == ALPHA_ISA + StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC())); +#elif THE_ISA == SPARC_ISA StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC())); +#endif if (instPtr->isMacroOp()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> |