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authorGabe Black <gblack@eecs.umich.edu>2006-10-05 16:26:16 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-05 16:26:16 -0400
commitd9172c8f462511cde474040581063180be18540a (patch)
tree9bff3f3dc9e1ea6d5ee18398d8ca543feb0eb4dc /src
parent51c8eab7b336a6c83e545b741cb975883fe56440 (diff)
downloadgem5-d9172c8f462511cde474040581063180be18540a.tar.xz
Partial reimplementation of the bus. The "clock" and "width" parameters have been added, and the HasData flag has been partially added to packets.
--HG-- extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39
Diffstat (limited to 'src')
-rw-r--r--src/mem/bus.cc41
-rw-r--r--src/mem/bus.hh16
-rw-r--r--src/mem/packet.hh23
-rw-r--r--src/python/m5/objects/Bus.py2
4 files changed, 68 insertions, 14 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index cf9e54e62..e3b395afc 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -78,6 +78,16 @@ Bus::recvTiming(Packet *pkt)
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
short dest = pkt->getDest();
+ //if (pkt->isRequest() && curTick < tickAddrLastUsed ||
+ // (pkt->isResponse() || pkt->hasData()) && curTick < tickDataLastUsed) {
+ //We're going to need resources that have already been committed
+ //Send this guy to the back of the line
+ //We don't need to worry about scheduling an event to deal with when the
+ //bus is freed because that's handled when tick*LastUsed is incremented.
+ // retryList.push_back(interfaces[pkt->getSrc()]);
+ // return false;
+ //}
+
if (dest == Packet::Broadcast) {
if ( timingSnoopPhase1(pkt) )
{
@@ -95,8 +105,29 @@ Bus::recvTiming(Packet *pkt)
assert(dest != pkt->getSrc()); // catch infinite loops
port = interfaces[dest];
}
+
+
if (port->sendTiming(pkt)) {
- // packet was successfully sent, just return true.
+ // Packet was successfully sent.
+ // Figure out what resources were used, and then return true.
+ //if (pkt->isRequest()) {
+ // The address bus will be used for one cycle
+ // while (tickAddrLastUsed <= curTick)
+ // tickAddrLastUsed += clock;
+ //}
+ //if (pkt->isResponse() || pkt->hasData()) {
+ // Use up the data bus for at least one bus cycle
+ // while (tickDataLastUsed <= curTick)
+ // tickDataLastUsed += clock;
+ // Use up the data bus for however many cycles remain
+ // if (pkt->hasData()) {
+ // int dataSize = pkt->getSize();
+ // for (int transmitted = width; transmitted < dataSize;
+ // transmitted += width) {
+ // tickDataLastUsed += clock;
+ // }
+ // }
+ //}
return true;
}
@@ -380,16 +411,20 @@ Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
Param<int> bus_id;
+ Param<int> clock;
+ Param<int> width;
END_DECLARE_SIM_OBJECT_PARAMS(Bus)
BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
- INIT_PARAM(bus_id, "a globally unique bus id")
+ INIT_PARAM(bus_id, "a globally unique bus id"),
+ INIT_PARAM(clock, "bus clock speed"),
+ INIT_PARAM(width, "width of the bus (bits)")
END_INIT_SIM_OBJECT_PARAMS(Bus)
CREATE_SIM_OBJECT(Bus)
{
- return new Bus(getInstanceName(), bus_id);
+ return new Bus(getInstanceName(), bus_id, clock, width);
}
REGISTER_SIM_OBJECT("Bus", Bus)
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 941389296..9dd666304 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -51,6 +51,14 @@ class Bus : public MemObject
{
/** a globally unique id for this bus. */
int busId;
+ /** the clock speed for the bus */
+ int clock;
+ /** the width of the bus in bits */
+ int width;
+ /** the last tick the address bus was used */
+ Tick tickAddrLastUsed;
+ /** the last tick the data bus was used */
+ Tick tickDataLastUsed;
static const int defaultId = -1;
@@ -199,8 +207,12 @@ class Bus : public MemObject
virtual void init();
- Bus(const std::string &n, int bus_id)
- : MemObject(n), busId(bus_id), defaultPort(NULL) {}
+ Bus(const std::string &n, int bus_id, int _clock, int _width)
+ : MemObject(n), busId(bus_id), clock(_clock), width(_width),
+ tickAddrLastUsed(0), tickDataLastUsed(0), defaultPort(NULL)
+ {
+ assert(width);
+ }
};
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index c7d28010c..b14343b47 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -174,7 +174,8 @@ class Packet
IsResponse = 1 << 5,
NeedsResponse = 1 << 6,
IsSWPrefetch = 1 << 7,
- IsHWPrefetch = 1 << 8
+ IsHWPrefetch = 1 << 8,
+ HasData = 1 << 9
};
public:
@@ -183,21 +184,24 @@ class Packet
{
InvalidCmd = 0,
ReadReq = IsRead | IsRequest | NeedsResponse,
- WriteReq = IsWrite | IsRequest | NeedsResponse,
- WriteReqNoAck = IsWrite | IsRequest,
- ReadResp = IsRead | IsResponse | NeedsResponse,
+ WriteReq = IsWrite | IsRequest | NeedsResponse,// | HasData,
+ WriteReqNoAck = IsWrite | IsRequest,// | HasData,
+ ReadResp = IsRead | IsResponse | NeedsResponse,// | HasData,
WriteResp = IsWrite | IsResponse | NeedsResponse,
- Writeback = IsWrite | IsRequest,
+ Writeback = IsWrite | IsRequest,// | HasData,
SoftPFReq = IsRead | IsRequest | IsSWPrefetch | NeedsResponse,
HardPFReq = IsRead | IsRequest | IsHWPrefetch | NeedsResponse,
- SoftPFResp = IsRead | IsResponse | IsSWPrefetch | NeedsResponse,
- HardPFResp = IsRead | IsResponse | IsHWPrefetch | NeedsResponse,
+ SoftPFResp = IsRead | IsResponse | IsSWPrefetch
+ | NeedsResponse,// | HasData,
+ HardPFResp = IsRead | IsResponse | IsHWPrefetch
+ | NeedsResponse,// | HasData,
InvalidateReq = IsInvalidate | IsRequest,
- WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
+ WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,// | HasData,
UpgradeReq = IsInvalidate | IsRequest | NeedsResponse,
UpgradeResp = IsInvalidate | IsResponse | NeedsResponse,
ReadExReq = IsRead | IsInvalidate | IsRequest | NeedsResponse,
- ReadExResp = IsRead | IsInvalidate | IsResponse | NeedsResponse
+ ReadExResp = IsRead | IsInvalidate | IsResponse
+ | NeedsResponse,// | HasData
};
/** Return the string name of the cmd field (for debugging and
@@ -219,6 +223,7 @@ class Packet
bool isResponse() { return (cmd & IsResponse) != 0; }
bool needsResponse() { return (cmd & NeedsResponse) != 0; }
bool isInvalidate() { return (cmd & IsInvalidate) != 0; }
+ bool hasData() { return (cmd & HasData) != 0; }
bool isCacheFill() { return (flags & CACHE_LINE_FILL) != 0; }
bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; }
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index f6828a0d5..b7c55990c 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -6,3 +6,5 @@ class Bus(MemObject):
port = VectorPort("vector port for connecting devices")
default = Port("Default port for requests that aren't handeled by a device.")
bus_id = Param.Int(0, "blah")
+ clock = Param.Clock("1GHz", "bus clock speed")
+ width = Param.Int(64, "bus width (bits)")