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authorGabe Black <gblack@eecs.umich.edu>2006-11-10 04:14:25 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-11-10 04:14:25 -0500
commitdc6af9fbf7bbbe29e431190867a2fed6fdcce8b5 (patch)
treeb471062212d6776535ccd9e68ef8d5e0879dbf94 /src
parent1d70dda6d72c4b563a19f3b4159a658d14b0eb41 (diff)
downloadgem5-dc6af9fbf7bbbe29e431190867a2fed6fdcce8b5.tar.xz
Set the ASI register to be something explicitly so that simulation is deterministic.
--HG-- extra : convert_revision : 38cd06f946fc0cc22288f71f567e77ce8fdfea99
Diffstat (limited to 'src')
-rw-r--r--src/arch/sparc/process.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index a3b7dde7c..11a799ccb 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -29,6 +29,7 @@
* Ali Saidi
*/
+#include "arch/sparc/asi.hh"
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/process.hh"
#include "base/loader/object_file.hh"
@@ -105,6 +106,8 @@ SparcLiveProcess::startup()
threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
//Set the trap level to 0
threadContexts[0]->setMiscReg(MISCREG_TL, 0);
+ //Set the ASI register to something fixed
+ threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
}
m5_auxv_t buildAuxVect(int64_t type, int64_t val)