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authorGabe Black <gblack@eecs.umich.edu>2008-12-06 14:48:59 -0800
committerGabe Black <gblack@eecs.umich.edu>2008-12-06 14:48:59 -0800
commite4790bcbe29b82dc81d4f34b78bb6ee2f718806a (patch)
tree005c22533afd21b3676067f9eb7086e6de5841b5 /src
parent489e3e7381993e5b34d83a839303cf204c4f53b6 (diff)
downloadgem5-e4790bcbe29b82dc81d4f34b78bb6ee2f718806a.tar.xz
X86: Add add_entry back in.
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/bios/IntelMP.py9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index 70e7963fa..758932180 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -86,6 +86,15 @@ class X86IntelMPConfigTable(SimObject):
ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
'extended configuration table entries')
+ def add_entry(self, entry):
+ if isinstance(entry, X86IntelMPBaseConfigEntry):
+ self.base_entries.append(entry)
+ elif isinstance(entry, X86IntelMPExtConfigEntry):
+ self.base_entries.append(entry)
+ else:
+ panic("Don't know what type of Intel MP entry %s is." \
+ % entry.__class__.__name__)
+
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'