summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAli Saidi <Ali.Saidi@ARM.com>2011-02-23 15:10:49 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2011-02-23 15:10:49 -0600
commit3de8e0a0d4acaee84760961089db623518b784f7 (patch)
tree1799a625d7457b2a7bd827681b283e7e2386aa40 /src
parent326191adc9ed16c672a7f2442055dc8a23626739 (diff)
downloadgem5-3de8e0a0d4acaee84760961089db623518b784f7.tar.xz
O3: If there is an outstanding table walk don't let the inst queue sleep.
If there is an outstanding table walk and no other activity in the CPU it can go to sleep and never wake up. This change makes the instruction queue always active if the CPU is waiting for a store to translate. If Gabe changes the way this code works then the below should be removed as indicated by the todo.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/inst_queue_impl.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index aa21a0edc..1a211af7a 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -880,7 +880,10 @@ InstructionQueue<Impl>::scheduleReadyInsts()
iqInstsIssued+= total_issued;
// If we issued any instructions, tell the CPU we had activity.
- if (total_issued || total_deferred_mem_issued) {
+ // @todo If the way deferred memory instructions are handeled due to
+ // translation changes then the deferredMemInsts condition should be removed
+ // from the code below.
+ if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
cpu->activityThisCycle();
} else {
DPRINTF(IQ, "Not able to schedule any instructions.\n");