X86: Start implementing the south bridge stuff.

--HG--
extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca

16 files changed, 933 insertions, 3 deletions

diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh
index d605ce218..f46279c81 100644
--- a/src/arch/x86/x86_traits.hh
+++ b/src/arch/x86/x86_traits.hh
@@ -90,6 +90,18 @@ namespace X86ISA
 
     const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
     const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
+
+    static inline Addr
+    x86IOAddress(const uint32_t port)
+    {
+        return PhysAddrPrefixIO | port;
+    }
+
+    static inline Addr
+    x86PciConfigAddress(const uint32_t addr)
+    {
+        return PhysAddrPrefixPciConfig | addr;
+    }
 }
 
 #endif //__ARCH_X86_X86TRAITS_HH__
diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py
index 3314e7741..86ae4c3ba 100644
--- a/src/dev/x86/PC.py
+++ b/src/dev/x86/PC.py
@@ -28,8 +28,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
 from Uart import Uart8250
+from Device import IsaFake
+from SouthBridge import SouthBridge
 from Platform import Platform
 from Pci import PciConfigAll
 from SimConsole import SimConsole
@@ -44,6 +45,11 @@ class PC(Platform):
 
     pciconfig = PciConfigAll()
 
+    south_bridge = SouthBridge()
+
+    # "Non-existant" port used for timing purposes by the linux kernel
+    i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
+
     # Serial port and console
     console = SimConsole()
     com_1 = Uart8250()
@@ -51,6 +57,8 @@ class PC(Platform):
     com_1.sim_console = console
 
     def attachIO(self, bus):
+        self.south_bridge.pio = bus.port
+        self.i_dont_exist.pio = bus.port
         self.com_1.pio = bus.port
         self.pciconfig.pio = bus.default
         bus.responder_set = True
diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript
index 6ebaed265..463344001 100644
--- a/src/dev/x86/SConscript
+++ b/src/dev/x86/SConscript
@@ -26,8 +26,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
-#          Gabe Black
+# Authors: Gabe Black
 
 Import('*')
 
diff --git a/src/dev/x86/south_bridge/SConscript b/src/dev/x86/south_bridge/SConscript
new file mode 100644
index 000000000..a7cb77b9b
--- /dev/null
+++ b/src/dev/x86/south_bridge/SConscript
@@ -0,0 +1,42 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+Import('*')
+
+if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
+    # Main device
+    SimObject('SouthBridge.py')
+    Source('south_bridge.cc')
+
+    # Sub devices
+    Source('cmos.cc')
+    Source('i8254.cc')
+    Source('i8259.cc')
+    Source('speaker.cc')
diff --git a/src/dev/x86/south_bridge/SouthBridge.py b/src/dev/x86/south_bridge/SouthBridge.py
new file mode 100644
index 000000000..bec3c4223
--- /dev/null
+++ b/src/dev/x86/south_bridge/SouthBridge.py
@@ -0,0 +1,35 @@
+# Copyright (c) 2008 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.params import *
+from m5.proxy import *
+from Device import PioDevice
+
+class SouthBridge(PioDevice):
+    type = 'SouthBridge'
+    pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
diff --git a/src/dev/x86/south_bridge/cmos.cc b/src/dev/x86/south_bridge/cmos.cc
new file mode 100644
index 000000000..43ada42e8
--- /dev/null
+++ b/src/dev/x86/south_bridge/cmos.cc
@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/cmos.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::Cmos::read(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        pkt->set(address);
+        break;
+      case 0x1:
+        pkt->set(readRegister(address));
+        break;
+      default:
+        panic("Read from undefined CMOS port.\n");
+    }
+    return latency;
+}
+
+Tick
+X86ISA::Cmos::write(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        address = pkt->get<uint8_t>();
+        break;
+      case 0x1:
+        writeRegister(address, pkt->get<uint8_t>());
+        break;
+      default:
+        panic("Write to undefined CMOS port.\n");
+    }
+    return latency;
+}
+
+uint8_t
+X86ISA::Cmos::readRegister(uint8_t reg)
+{
+    assert(reg < numRegs);
+    switch(reg)
+    {
+      case 0x0:
+      case 0x1:
+      case 0x2:
+      case 0x3:
+      case 0x4:
+      case 0x5:
+      case 0x6:
+      case 0x7:
+      case 0x8:
+      case 0x9:
+      case 0xA:
+      case 0xB:
+      case 0xC:
+      case 0xD:
+        warn("Reading RTC in the CMOS.\n");
+        break;
+      default:
+        warn("Reading non-volitile CMOS address %x as %x.\n", reg, regs[reg]);
+        break;
+    }
+    return regs[reg];
+}
+
+void
+X86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val)
+{
+    assert(reg < numRegs);
+    switch(reg)
+    {
+      case 0x0:
+      case 0x1:
+      case 0x2:
+      case 0x3:
+      case 0x4:
+      case 0x5:
+      case 0x6:
+      case 0x7:
+      case 0x8:
+      case 0x9:
+      case 0xA:
+      case 0xB:
+      case 0xC:
+      case 0xD:
+        warn("Writing RTC in the CMOS.\n");
+        break;
+      default:
+        warn("Writing non-volitile CMOS address %x with %x.\n", reg, val);
+        break;
+    }
+    regs[reg] = val;
+}
diff --git a/src/dev/x86/south_bridge/cmos.hh b/src/dev/x86/south_bridge/cmos.hh
new file mode 100644
index 000000000..cd3fab280
--- /dev/null
+++ b/src/dev/x86/south_bridge/cmos.hh
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+#define __DEV_X86_SOUTH_BRIDGE_CMOS_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class Cmos : public SubDevice
+{
+  protected:
+    uint8_t address;
+
+    static const int numRegs = 128;
+
+    uint8_t regs[numRegs];
+
+    uint8_t readRegister(uint8_t reg);
+    void writeRegister(uint8_t reg, uint8_t val);
+
+  public:
+
+    Cmos()
+    {
+        memset(regs, 0, numRegs * sizeof(uint8_t));
+        address = 0;
+    }
+
+    Cmos(Tick _latency) : SubDevice(_latency)
+    {
+        memset(regs, 0, numRegs * sizeof(uint8_t));
+        address = 0;
+    }
+
+    Cmos(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {
+        memset(regs, 0, numRegs * sizeof(uint8_t));
+        address = 0;
+    }
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_CMOS_HH__
diff --git a/src/dev/x86/south_bridge/i8254.cc b/src/dev/x86/south_bridge/i8254.cc
new file mode 100644
index 000000000..fb6723a51
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8254.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/i8254.hh"
+#include "mem/packet_access.hh"
+
+Tick
+X86ISA::I8254::read(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        warn("Reading from timer 0 counter.\n");
+        break;
+      case 0x1:
+        warn("Reading from timer 1 counter.\n");
+        break;
+      case 0x2:
+        warn("Reading from timer 2 counter.\n");
+        break;
+      case 0x3:
+        fatal("Reading from timer control word which is read only.\n");
+        break;
+      default:
+        panic("Read from undefined i8254 register.\n");
+    }
+    return SubDevice::read(pkt);
+}
+
+Tick
+X86ISA::I8254::write(PacketPtr pkt)
+{
+    assert(pkt->getSize() == 1);
+    switch(pkt->getAddr() - addrRange.start)
+    {
+      case 0x0:
+        warn("Writing to timer 0 counter.\n");
+        break;
+      case 0x1:
+        warn("Writing to timer 1 counter.\n");
+        break;
+      case 0x2:
+        warn("Writing to timer 2 counter.\n");
+        break;
+      case 0x3:
+        processControlWord(pkt->get<uint8_t>());
+        return latency;
+      default:
+        panic("Write to undefined i8254 register.\n");
+    }
+    return SubDevice::write(pkt);
+}
+
+void
+X86ISA::I8254::processControlWord(uint8_t word)
+{
+    warn("I8254 received control word %x.\n", word);
+}
diff --git a/src/dev/x86/south_bridge/i8254.hh b/src/dev/x86/south_bridge/i8254.hh
new file mode 100644
index 000000000..f246fd8e4
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8254.hh
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_I8254_HH__
+#define __DEV_X86_SOUTH_BRIDGE_I8254_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class I8254 : public SubDevice
+{
+  protected:
+    void processControlWord(uint8_t word);
+
+  public:
+
+    I8254()
+    {}
+    I8254(Tick _latency) : SubDevice(_latency)
+    {}
+    I8254(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {}
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8254_HH__
diff --git a/src/dev/x86/south_bridge/i8259.cc b/src/dev/x86/south_bridge/i8259.cc
new file mode 100644
index 000000000..0cf83dece
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8259.cc
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "dev/x86/south_bridge/i8259.hh"
+
+Tick
+X86ISA::I8259::read(PacketPtr pkt)
+{
+    warn("Reading from PIC device.\n");
+    return SubDevice::read(pkt);
+}
+
+Tick
+X86ISA::I8259::write(PacketPtr pkt)
+{
+    warn("Writing to PIC device.\n");
+    return SubDevice::write(pkt);
+}
diff --git a/src/dev/x86/south_bridge/i8259.hh b/src/dev/x86/south_bridge/i8259.hh
new file mode 100644
index 000000000..3fda75dfb
--- /dev/null
+++ b/src/dev/x86/south_bridge/i8259.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_I8259_HH__
+#define __DEV_X86_SOUTH_BRIDGE_I8259_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class I8259 : public SubDevice
+{
+  public:
+
+    I8259()
+    {}
+    I8259(Tick _latency) : SubDevice(_latency)
+    {}
+    I8259(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {}
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_I8259_HH__
diff --git a/src/dev/x86/south_bridge/south_bridge.cc b/src/dev/x86/south_bridge/south_bridge.cc
new file mode 100644
index 000000000..f25b3b811
--- /dev/null
+++ b/src/dev/x86/south_bridge/south_bridge.cc
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/south_bridge.hh"
+
+using namespace X86ISA;
+
+void
+SouthBridge::addDevice(X86ISA::SubDevice & sub)
+{
+    rangeList.push_back(sub.addrRange);
+    rangeMap.insert(sub.addrRange, &sub);
+}
+
+void
+SouthBridge::addressRanges(AddrRangeList &range_list)
+{
+    range_list = rangeList;
+}
+
+Tick
+SouthBridge::read(PacketPtr pkt)
+{
+    RangeMapIt sub =
+        rangeMap.find(RangeSize(pkt->getAddr(), 1));
+    assert(sub != rangeMap.end());
+    return sub->second->read(pkt);
+}
+
+Tick
+SouthBridge::write(PacketPtr pkt)
+{
+    RangeMapIt sub =
+        rangeMap.find(RangeSize(pkt->getAddr(), 1));
+    assert(sub != rangeMap.end());
+    return sub->second->write(pkt);
+}
+
+SouthBridge::SouthBridge(const Params *p) : PioDevice(p),
+    pic1(0x20, 2, p->pio_latency),
+    pic2(0xA0, 2, p->pio_latency),
+    pit(0x40, 4, p->pio_latency),
+    cmos(0x70, 2, p->pio_latency),
+    speaker(0x61, 1, p->pio_latency)
+{
+    addDevice(pic1);
+    addDevice(pic2);
+    addDevice(pit);
+    addDevice(cmos);
+    addDevice(speaker);
+}
+
+SouthBridge *
+SouthBridgeParams::create()
+{
+    return new SouthBridge(this);
+}
diff --git a/src/dev/x86/south_bridge/south_bridge.hh b/src/dev/x86/south_bridge/south_bridge.hh
new file mode 100644
index 000000000..28936fb91
--- /dev/null
+++ b/src/dev/x86/south_bridge/south_bridge.hh
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
+
+#include "base/range_map.hh"
+#include "dev/io_device.hh"
+#include "dev/x86/south_bridge/cmos.hh"
+#include "dev/x86/south_bridge/i8254.hh"
+#include "dev/x86/south_bridge/i8259.hh"
+#include "dev/x86/south_bridge/speaker.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+#include "params/SouthBridge.hh"
+
+class SouthBridge : public PioDevice
+{
+  protected:
+    // PICs
+    X86ISA::I8259 pic1;
+    X86ISA::I8259 pic2;
+
+    // I8254 Programmable Interval Timer
+    X86ISA::I8254 pit;
+
+    // CMOS apperature
+    X86ISA::Cmos cmos;
+
+    // PC speaker
+    X86ISA::Speaker speaker;
+
+    AddrRangeList rangeList;
+
+    typedef range_map<Addr, X86ISA::SubDevice *> RangeMap;
+    typedef RangeMap::iterator RangeMapIt;
+    RangeMap rangeMap;
+
+
+    void addDevice(X86ISA::SubDevice &);
+
+  public:
+    void addressRanges(AddrRangeList &range_list);
+
+    Tick read(PacketPtr pkt);
+    Tick write(PacketPtr pkt);
+
+    typedef SouthBridgeParams Params;
+    SouthBridge(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+};
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SOUTH_BRIDGE_HH__
diff --git a/src/dev/x86/south_bridge/speaker.cc b/src/dev/x86/south_bridge/speaker.cc
new file mode 100644
index 000000000..734dba4c2
--- /dev/null
+++ b/src/dev/x86/south_bridge/speaker.cc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "base/bitunion.hh"
+#include "dev/x86/south_bridge/speaker.hh"
+#include "mem/packet_access.hh"
+
+BitUnion8(SpeakerControl)
+    Bitfield<0> gate;
+    Bitfield<1> speaker;
+    Bitfield<5> timer;
+EndBitUnion(SpeakerControl)
+
+Tick
+X86ISA::Speaker::read(PacketPtr pkt)
+{
+    assert(pkt->getAddr() == addrRange.start);
+    assert(pkt->getSize() == 1);
+    SpeakerControl val = 0xFF;
+    warn("Reading from speaker device: gate %s, speaker %s, output %s.\n",
+            val.gate ? "on" : "off",
+            val.speaker ? "on" : "off",
+            val.timer ? "on" : "off");
+    pkt->set((uint8_t)val);
+    return latency;
+}
+
+Tick
+X86ISA::Speaker::write(PacketPtr pkt)
+{
+    assert(pkt->getAddr() == addrRange.start);
+    assert(pkt->getSize() == 1);
+    SpeakerControl val = pkt->get<uint8_t>();
+    warn("Writing to speaker device: gate %s, speaker %s.\n",
+            val.gate ? "on" : "off", val.speaker ? "on" : "off");
+    return latency;
+}
diff --git a/src/dev/x86/south_bridge/speaker.hh b/src/dev/x86/south_bridge/speaker.hh
new file mode 100644
index 000000000..df738e42b
--- /dev/null
+++ b/src/dev/x86/south_bridge/speaker.hh
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "dev/x86/south_bridge/sub_device.hh"
+
+namespace X86ISA
+{
+
+class Speaker : public SubDevice
+{
+  public:
+
+    Speaker()
+    {}
+    Speaker(Tick _latency) : SubDevice(_latency)
+    {}
+    Speaker(Addr start, Addr size, Tick _latency) :
+        SubDevice(start, size, _latency)
+    {}
+
+    Tick read(PacketPtr pkt);
+
+    Tick write(PacketPtr pkt);
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SPEAKER_HH__
diff --git a/src/dev/x86/south_bridge/sub_device.hh b/src/dev/x86/south_bridge/sub_device.hh
new file mode 100644
index 000000000..3cc51bdd9
--- /dev/null
+++ b/src/dev/x86/south_bridge/sub_device.hh
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
+#define __DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "base/range.hh"
+#include "mem/packet.hh"
+
+namespace X86ISA
+{
+
+class SubDevice
+{
+  public:
+
+    Range<Addr> addrRange;
+    Tick latency;
+
+    virtual
+    ~SubDevice()
+    {}
+
+    SubDevice()
+    {}
+    SubDevice(Tick _latency) : latency(_latency)
+    {}
+    SubDevice(Addr start, Addr size, Tick _latency) :
+        addrRange(RangeSize(x86IOAddress(start), size)), latency(_latency)
+    {}
+
+    virtual Tick
+    read(PacketPtr pkt)
+    {
+        assert(pkt->getSize() <= 4);
+        pkt->allocate();
+        const uint32_t neg1 = -1;
+        pkt->setData((uint8_t *)(&neg1));
+        return latency;
+    }
+
+    virtual Tick
+    write(PacketPtr pkt)
+    {
+        return latency;
+    }
+};
+
+}; // namespace X86ISA
+
+#endif //__DEV_X86_SOUTH_BRIDGE_SUB_DEVICE_HH__