summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorRon Dreslinski <rdreslin@umich.edu>2006-10-08 19:05:48 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-10-08 19:05:48 -0400
commite65f0cef3ca70edf37ff74920def4ac899f6c7e3 (patch)
tree975e458e2e1c5e566810abdfb27375679ff95867 /src
parent8a539a774ff3ae701e2aa4daae96b5d988c74409 (diff)
downloadgem5-e65f0cef3ca70edf37ff74920def4ac899f6c7e3.tar.xz
Only respond if the pkt needs a response.
Fix an issue with memory handling writebacks. src/mem/cache/base_cache.hh: src/mem/tport.cc: Only respond if the pkt needs a response. src/mem/physical.cc: Make physical memory respond to writebacks, set satisfied for invalidates/upgrades. --HG-- extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/base_cache.hh13
-rw-r--r--src/mem/physical.cc15
-rw-r--r--src/mem/tport.cc8
3 files changed, 23 insertions, 13 deletions
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 4b0e114b9..2e92e7730 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -516,8 +516,10 @@ class BaseCache : public MemObject
*/
void respond(Packet *pkt, Tick time)
{
- CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
- reqCpu->schedule(time);
+ if (pkt->needsResponse()) {
+ CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+ reqCpu->schedule(time);
+ }
}
/**
@@ -530,8 +532,10 @@ class BaseCache : public MemObject
if (!pkt->req->isUncacheable()) {
missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
}
- CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
- reqCpu->schedule(time);
+ if (pkt->needsResponse()) {
+ CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
+ reqCpu->schedule(time);
+ }
}
/**
@@ -542,6 +546,7 @@ class BaseCache : public MemObject
{
// assert("Implement\n" && 0);
// mi->respond(pkt,curTick + hitLatency);
+ assert (pkt->needsResponse());
CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
reqMem->schedule(time);
}
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 23b1d5ffc..070693442 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -197,22 +197,25 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
{
assert(pkt->getAddr() + pkt->getSize() < params()->addrRange.size());
- switch (pkt->cmd) {
- case Packet::ReadReq:
+ if (pkt->isRead()) {
if (pkt->req->isLocked()) {
trackLoadLocked(pkt->req);
}
memcpy(pkt->getPtr<uint8_t>(),
pmemAddr + pkt->getAddr() - params()->addrRange.start,
pkt->getSize());
- break;
- case Packet::WriteReq:
+ }
+ else if (pkt->isWrite()) {
if (writeOK(pkt->req)) {
memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
pkt->getPtr<uint8_t>(), pkt->getSize());
}
- break;
- default:
+ }
+ else if (pkt->isInvalidate()) {
+ //upgrade or invalidate
+ pkt->flags |= SATISFIED;
+ }
+ else {
panic("unimplemented");
}
diff --git a/src/mem/tport.cc b/src/mem/tport.cc
index 55c301c87..cef7a2a5b 100644
--- a/src/mem/tport.cc
+++ b/src/mem/tport.cc
@@ -47,9 +47,11 @@ SimpleTimingPort::recvTiming(Packet *pkt)
// if we ever added it back.
assert(pkt->result != Packet::Nacked);
Tick latency = recvAtomic(pkt);
- // turn packet around to go back to requester
- pkt->makeTimingResponse();
- sendTimingLater(pkt, latency);
+ // turn packet around to go back to requester if response expected
+ if (pkt->needsResponse()) {
+ pkt->makeTimingResponse();
+ sendTimingLater(pkt, latency);
+ }
return true;
}