diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:56 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:56 -0400 |
| commit | ea402970185d5df01dbad2c0f41b8d76d2eb01cd (patch) | |
| tree | ca6670c9db05e67783b34a4a1d099b9500ef2bdd /src | |
| parent | bb1d2f39575795f0b369bb3cabb52c9d42a8b1c6 (diff) | |
| download | gem5-ea402970185d5df01dbad2c0f41b8d76d2eb01cd.tar.xz | |
cpu: Move the branch predictor out of the BaseCPU
The branch predictor is guarded by having either the in-order or
out-of-order CPU as one of the available CPU models and therefore
should not be used in the BaseCPU. This patch moves the parameter to
the relevant CPU classes.
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/BaseCPU.py | 3 | ||||
| -rw-r--r-- | src/cpu/inorder/InOrderCPU.py | 4 | ||||
| -rw-r--r-- | src/cpu/o3/O3CPU.py | 4 |
3 files changed, 6 insertions, 5 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 7ec79ad0a..cd82207cd 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -51,7 +51,6 @@ from Bus import CoherentBus from InstTracer import InstTracer from ExeTracer import ExeTracer from MemObject import MemObject -from BranchPredictor import BranchPredictor from ClockDomain import * default_tracer = ExeTracer() @@ -210,8 +209,6 @@ class BaseCPU(MemObject): dcache_port = MasterPort("Data Port") _cached_ports = ['icache_port', 'dcache_port'] - branchPred = Param.BranchPredictor(NULL, "Branch Predictor") - if buildEnv['TARGET_ISA'] in ['x86', 'arm']: _cached_ports += ["itb.walker.port", "dtb.walker.port"] diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py index e29a29556..4caf254c4 100644 --- a/src/cpu/inorder/InOrderCPU.py +++ b/src/cpu/inorder/InOrderCPU.py @@ -68,4 +68,6 @@ class InOrderCPU(BaseCPU): div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations") div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations") - branchPred = BranchPredictor(numThreads = Parent.numThreads) + branchPred = Param.BranchPredictor(BranchPredictor(numThreads = + Parent.numThreads), + "Branch Predictor") diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index f46388b4c..e19881248 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -125,7 +125,9 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - branchPred = BranchPredictor(numThreads = Parent.numThreads) + branchPred = Param.BranchPredictor(BranchPredictor(numThreads = + Parent.numThreads), + "Branch Predictor") needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', "Enable TSO Memory model") |