Make Sparc traceflag even more chatty

some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct

src/arch/sparc/floatregfile.cc:
    Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
    add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
    some fixes to fp instructions to use the single precision registers
    fix smul again
    fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
    if this is an fp op emit fp check code
src/cpu/exetrace.cc:
    check fp regs as well as int regs
src/cpu/m5legion_interface.h:
    add fpregs to m5legion struct

--HG--
extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232

7 files changed, 82 insertions, 43 deletions

diff --git a/src/arch/sparc/floatregfile.cc b/src/arch/sparc/floatregfile.cc
index 7f3d5a758..1bb78c67b 100644
--- a/src/arch/sparc/floatregfile.cc
+++ b/src/arch/sparc/floatregfile.cc
@@ -72,16 +72,19 @@ FloatReg FloatRegFile::readReg(int floatReg, int width)
         float32_t result32;
         memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
         result = htog(result32);
+        DPRINTF(Sparc, "Read FP32 register %d = 0x%x\n", floatReg, result);
         break;
       case DoubleWidth:
         float64_t result64;
         memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
         result = htog(result64);
+        DPRINTF(Sparc, "Read FP64 register %d = 0x%x\n", floatReg, result);
         break;
       case QuadWidth:
         float128_t result128;
         memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
         result = htog(result128);
+        DPRINTF(Sparc, "Read FP128 register %d = 0x%x\n", floatReg, result);
         break;
       default:
         panic("Attempted to read a %d bit floating point register!", width);
@@ -101,16 +104,19 @@ FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
         uint32_t result32;
         memcpy(&result32, regSpace + 4 * floatReg, sizeof(result32));
         result = htog(result32);
+        DPRINTF(Sparc, "Read FP32 bits register %d = 0x%x\n", floatReg, result);
         break;
       case DoubleWidth:
         uint64_t result64;
         memcpy(&result64, regSpace + 4 * floatReg, sizeof(result64));
         result = htog(result64);
+        DPRINTF(Sparc, "Read FP64 bits register %d = 0x%x\n", floatReg, result);
         break;
       case QuadWidth:
         uint64_t result128;
         memcpy(&result128, regSpace + 4 * floatReg, sizeof(result128));
         result = htog(result128);
+        DPRINTF(Sparc, "Read FP128 bits register %d = 0x%x\n", floatReg, result);
         break;
       default:
         panic("Attempted to read a %d bit floating point register!", width);
diff --git a/src/arch/sparc/isa/base.isa b/src/arch/sparc/isa/base.isa
index 4a806bfd0..5b65ec288 100644
--- a/src/arch/sparc/isa/base.isa
+++ b/src/arch/sparc/isa/base.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -290,3 +290,27 @@ output decoder {{
         }
 }};
 
+output exec {{
+    /// Check "FP enabled" machine status bit.  Called when executing any FP
+    /// instruction in full-system mode.
+    /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
+    /// if not.  Non-full-system mode: always returns NoFault.
+#if FULL_SYSTEM
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        Fault fault = NoFault;	// dummy... this ipr access should not fault
+        if (xc->readMiscRegWithEffect(MISCREG_PSTATE) & PSTATE::pef &&
+            xc->readMiscRegWithEffect(MISCREG_FPRS) & 0x4)
+            return NoFault;
+        else
+            return new FpDisabled;
+    }
+#else
+    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    {
+        return NoFault;
+    }
+#endif
+}};
+
+
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 425ebc9d0..852fddfcf 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -186,7 +186,7 @@ decode OP default Unknown::unknown()
                 Y = Rd<63:32>;
             }});
             0x0B: smul({{
-                Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
+                Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
                 Y = Rd.sdw<63:32>;
             }});
             0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
@@ -246,8 +246,7 @@ decode OP default Unknown::unknown()
                 Rd = resTemp = Rs1 + val2 + carryin;}},
                 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
                 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                {{(Rs1<63:1> + val2<63:1> +
-                    ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
+                {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );
             0x1A: umulcc({{
@@ -257,16 +256,16 @@ decode OP default Unknown::unknown()
                 {{0}},{{0}},{{0}},{{0}});
             0x1B: smulcc({{
                 int64_t resTemp;
-                Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
+                Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
                 Y = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1C: subccc({{
                 int64_t resTemp, val2 = Rs2_or_imm13;
                 int64_t carryin = Ccr<0:0>;
                 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
-                {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
+                {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
                 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
+                {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
                 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
             );
             0x1D: udivxcc({{
@@ -664,7 +663,7 @@ decode OP default Unknown::unknown()
                         Fsr &= ~(7 << 14);
                         Fsr &= ~(0x1F);
                     }});
-                    0x03: Trap::fmovq({{fault = new FpDisabled;}});
+                    0x03: Trap::fmovq({{fault = new FpExceptionOther;}});
                     0x05: fnegs({{
                         Frds.uw = Frs2s.uw ^ (1UL << 31);
                         //fsr.ftt = fsr.cexc = 0
@@ -860,11 +859,11 @@ decode OP default Unknown::unknown()
                 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
                 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
                 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
-                0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
+                0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
                 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
                 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
                 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
-                0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
+                0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
                 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
                 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
                 0x7C: Trap::for({{fault = new IllegalInstruction;}});
@@ -1130,14 +1129,14 @@ decode OP default Unknown::unknown()
             {{ Mem.uw = Rd.uw;
                Rd.uw = uReg0;}}, {{EXT_ASI}});
         format Trap {
-            0x20: Load::ldf({{Frd.uw = Mem.uw;}});
+            0x20: Load::ldf({{Frds.uw = Mem.uw;}});
             0x21: decode X {
                 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
                 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
             }
             0x22: ldqf({{fault = new FpDisabled;}});
             0x23: Load::lddf({{Frd.udw = Mem.udw;}});
-            0x24: Store::stf({{Mem.uw = Frd.uw;}});
+            0x24: Store::stf({{Mem.uw = Frds.uw;}});
             0x25: decode X {
                 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
                 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
@@ -1145,7 +1144,7 @@ decode OP default Unknown::unknown()
             0x26: stqf({{fault = new FpDisabled;}});
             0x27: Store::stdf({{Mem.udw = Frd.udw;}});
             0x2D: Nop::prefetch({{ }});
-            0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
+            0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
             0x32: ldqfa({{fault = new FpDisabled;}});
             format LoadAlt {
                 0x33: decode EXT_ASI {
@@ -1228,7 +1227,7 @@ decode OP default Unknown::unknown()
                         {{fault = new DataAccessException;}});
                 }
             }
-            0x34: Store::stfa({{Mem.uw = Frd.uw;}});
+            0x34: Store::stfa({{Mem.uw = Frds.uw;}});
             0x36: stqfa({{fault = new FpDisabled;}});
             format StoreAlt {
                 0x37: decode EXT_ASI {
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index a4c05387b..db6efd229 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -71,6 +71,7 @@ def template BasicExecute {{
         {
             Fault fault = NoFault;
 
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(code)s;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index b6e0945b7..3b02f58de 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -141,6 +141,7 @@ def template LoadExecute {{
         {
             Fault fault = NoFault;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
@@ -169,6 +170,7 @@ def template LoadExecute {{
             Fault fault = NoFault;
             Addr EA;
             uint%(mem_acc_size)s_t Mem;
+            %(fp_enable_check)s;
             %(ea_decl)s;
             %(ea_rd)s;
             %(ea_code)s;
@@ -206,6 +208,7 @@ def template StoreExecute {{
             //It should be optomized out in all the others
             bool storeCond = true;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
@@ -235,6 +238,7 @@ def template StoreExecute {{
             Fault fault = NoFault;
             bool storeCond = true;
             Addr EA;
+            %(fp_enable_check)s;
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 26e8b6b44..9ea90681c 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -293,7 +293,8 @@ Trace::InstRecord::dump(ostream &outs)
         bool diffPC   = false;
         bool diffCC   = false;
         bool diffInst = false;
-        bool diffRegs = false;
+        bool diffIntRegs = false;
+        bool diffFpRegs = false;
         bool diffTpc = false;
         bool diffTnpc = false;
         bool diffTstate = false;
@@ -357,10 +358,15 @@ Trace::InstRecord::dump(ostream &outs)
                     }
                     for (int i = 0; i < TheISA::NumIntArchRegs; i++) {
                         if (thread->readIntReg(i) != shared_data->intregs[i]) {
-                            diffRegs = true;
+                            diffIntRegs = true;
                         }
                     }
-                    uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
+                    for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
+                        if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
+                            diffFpRegs = true;
+                        }
+                    }
+                            uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
                     if (oldTl != shared_data->tl)
                         diffTl = true;
                     for (int i = 1; i <= MaxTL; i++) {
@@ -426,12 +432,12 @@ Trace::InstRecord::dump(ostream &outs)
                                 diffTlb = true;
                     }
 
-                    if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
-                            diffTnpc || diffTstate || diffTt || diffHpstate ||
-                            diffHtstate || diffHtba || diffPstate || diffY ||
-                            diffCcr || diffTl || diffGl || diffAsi || diffPil ||
-                            diffCwp || diffCansave || diffCanrestore ||
-                            diffOtherwin || diffCleanwin || diffTlb)
+                    if ((diffPC || diffCC || diffInst || diffIntRegs ||
+                         diffFpRegs || diffTpc || diffTnpc || diffTstate ||
+                         diffTt || diffHpstate || diffHtstate || diffHtba ||
+                         diffPstate || diffY || diffCcr || diffTl || diffGl ||
+                         diffAsi || diffPil || diffCwp || diffCansave ||
+                         diffCanrestore || diffOtherwin || diffCleanwin || diffTlb)
                         && !((staticInst->machInst & 0xC1F80000) == 0x81D00000)
                         && !(((staticInst->machInst & 0xC0000000) == 0xC0000000)
                             && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1)
@@ -444,8 +450,10 @@ Trace::InstRecord::dump(ostream &outs)
                             outs << " [CC]";
                         if (diffInst)
                             outs << " [Instruction]";
-                        if (diffRegs)
+                        if (diffIntRegs)
                             outs << " [IntRegs]";
+                        if (diffFpRegs)
+                            outs << " [FpRegs]";
                         if (diffTpc)
                             outs << " [Tpc]";
                         if (diffTnpc)
@@ -588,26 +596,22 @@ Trace::InstRecord::dump(ostream &outs)
 
                         printSectionHeader(outs, "General Purpose Registers");
                         static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
-                        for(int y = 0; y < 4; y++)
-                        {
-                            for(int x = 0; x < 8; x++)
-                            {
+                        for(int y = 0; y < 4; y++) {
+                            for(int x = 0; x < 8; x++) {
                                 char label[8];
                                 sprintf(label, "%s%d", regtypes[y], x);
                                 printRegPair(outs, label,
                                         thread->readIntReg(y*8+x),
                                         shared_data->intregs[y*8+x]);
-                                /*outs << regtypes[y] << x << "         " ;
-                                outs <<  "0x" << hex << setw(16)
-                                    << thread->readIntReg(y*8+x);
-                                if (thread->readIntReg(y*8 + x)
-                                        != shared_data->intregs[y*8+x])
-                                    outs << "     X     ";
-                                else
-                                    outs << "     |     ";
-                                outs << "0x" << setw(16) << hex
-                                    << shared_data->intregs[y*8+x]
-                                    << endl;*/
+                            }
+                        }
+                        if (diffFpRegs) {
+                            for (int x = 0; x < 32; x++) {
+                                char label[8];
+                                sprintf(label, "%%f%d", x);
+                                printRegPair(outs, label,
+                                 thread->readFloatRegBits(x,FloatRegFile::DoubleWidth),
+                                 shared_data->fpregs[x]);
                             }
                         }
                         if (diffTlb) {
diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h
index c3ba5986e..81714f769 100644
--- a/src/cpu/m5legion_interface.h
+++ b/src/cpu/m5legion_interface.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -30,7 +30,7 @@
 
 #include <unistd.h>
 
-#define VERSION         0xA1000007
+#define VERSION         0xA1000008
 #define OWN_M5          0x000000AA
 #define OWN_LEGION      0x00000055
 
@@ -47,6 +47,7 @@ typedef struct {
     uint32_t instruction;
     uint32_t new_instruction;
     uint64_t intregs[32];
+    uint64_t fpregs[32];
 
     uint64_t tpc[8];
     uint64_t tnpc[8];