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authorRon Dreslinski <rdreslin@umich.edu>2006-07-05 15:13:27 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-07-05 15:13:27 -0400
commit4201ec84b2dd7d96148bf661124dd7b5d0e7204b (patch)
tree1886edde38b2da28cb45f4e13135b1993502f45d /src
parentf4c5609988731f52f9c5bd84ee2db364bbf6fd97 (diff)
downloadgem5-4201ec84b2dd7d96148bf661124dd7b5d0e7204b.tar.xz
Fix some unset values in the request in the timing CPU.
Properly implement the MSHR allocate function. src/cpu/simple/timing.cc: Set the thread context in the CPU. Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution. src/mem/cache/miss/mshr.cc: Properly implement the allocate function for the MSHR. --HG-- extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
Diffstat (limited to 'src')
-rw-r--r--src/cpu/simple/timing.cc4
-rw-r--r--src/mem/cache/miss/mshr.cc36
2 files changed, 21 insertions, 19 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 0729f9489..d5bdcfa9b 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -207,7 +207,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
// need to fill in CPU & thread IDs here
Request *data_read_req = new Request();
-
+ data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
if (traceData) {
@@ -288,6 +288,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
// need to fill in CPU & thread IDs here
Request *data_write_req = new Request();
+ data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
// translate to physical address
@@ -371,6 +372,7 @@ TimingSimpleCPU::fetch()
// need to fill in CPU & thread IDs here
Request *ifetch_req = new Request();
+ ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
Fault fault = setupFetchRequest(ifetch_req);
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 05a2fe1c5..1a85d3018 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -57,26 +57,26 @@ void
MSHR::allocate(Packet::Command cmd, Addr _addr, int _asid, int size,
Packet * &target)
{
- assert("NEED TO FIX YET\n" && 0);
-#if 0
- assert(targets.empty());
- addr = _addr;
- asid = _asid;
-
- pkt = new Packet(); // allocate new memory request
- pkt->addr = addr; //picked physical address for now
- pkt->cmd = cmd;
- pkt->size = size;
- pkt->data = new uint8_t[size];
- pkt->senderState = this;
- //Set the time here for latency calculations
- pkt->time = curTick;
-
- if (target) {
- pkt->req = target->req;
+ if (target)
+ {
+ //Have a request, just use it
+ pkt = new Packet(target->req, cmd, Packet::Broadcast, size);
+ pkt->time = curTick;
+ pkt->allocate();
+ pkt->senderState = (Packet::SenderState *)this;
allocateTarget(target);
}
-#endif
+ else
+ {
+ //need a request first
+ Request * req = new Request();
+ req->setPhys(addr, size, 0);
+ //Thread context??
+ pkt = new Packet(req, cmd, Packet::Broadcast, size);
+ pkt->time = curTick;
+ pkt->allocate();
+ pkt->senderState = (Packet::SenderState *)this;
+ }
}
// Since we aren't sure if data is being used, don't copy here.