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authorGabe Black <gblack@eecs.umich.edu>2009-07-20 20:14:15 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-20 20:14:15 -0700
commit5161bc19d9ce5199ec48a6f57c4d058a6db6cb15 (patch)
tree06bd63f9edf9b5f28dbac29dfa60f0d9056a2004 /src
parent225de2eaff57bdf27d367531f25a654e4cd06fe6 (diff)
downloadgem5-5161bc19d9ce5199ec48a6f57c4d058a6db6cb15.tar.xz
MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
Diffstat (limited to 'src')
-rwxr-xr-xsrc/arch/mips/dt_constants.hh269
-rw-r--r--src/arch/mips/isa.cc301
-rw-r--r--src/arch/mips/isa/decoder.isa528
-rw-r--r--src/arch/mips/isa/formats/mt.isa27
-rw-r--r--src/arch/mips/isa/operands.isa39
-rwxr-xr-xsrc/arch/mips/mt.hh170
-rwxr-xr-xsrc/arch/mips/mt_constants.hh140
-rwxr-xr-xsrc/arch/mips/pra_constants.hh737
8 files changed, 960 insertions, 1251 deletions
diff --git a/src/arch/mips/dt_constants.hh b/src/arch/mips/dt_constants.hh
index a836c86da..64b1cf232 100755
--- a/src/arch/mips/dt_constants.hh
+++ b/src/arch/mips/dt_constants.hh
@@ -32,184 +32,105 @@
#define __ARCH_MIPS_DT_CONSTANTS_HH__
#include "arch/mips/types.hh"
+#include "base/bitunion.hh"
namespace MipsISA
{
- // See the EJTAG Specification - Revision 4.10
- // Also see PDTrace Specification - Revision 4.30
-
- // Debug Register - CP0 Reg 23, Sel 0
- const unsigned Debug_DBD = 31;
- const unsigned Debug_DM_HI = 30;
- const unsigned Debug_DM_LO = 30;
- const unsigned Debug_NODCR = 29;
- const unsigned Debug_LSNM = 28;
- const unsigned Debug_DOZE = 27;
- const unsigned Debug_HALT = 26;
- const unsigned Debug_COUNTDM = 25;
- const unsigned Debug_IBUSEP = 24;
- const unsigned Debug_MCHECKEP = 23;
- const unsigned Debug_CACHEEP = 22;
- const unsigned Debug_DBUSEP = 21;
- const unsigned Debug_IEXI_HI = 20;
- const unsigned Debug_IEXI_LO = 20;
- const unsigned Debug_DDBS_IMPR = 19;
- const unsigned Debug_DDBL_IMPR = 18;
- const unsigned Debug_EJTAGVER_2 =17;
- const unsigned Debug_EJTAGVER_1 =16;
- const unsigned Debug_EJTAGVER_0 =15;
- const unsigned Debug_EJTAGVER_HI = 17;
- const unsigned Debug_EJTAGVER_LO = 15;
- const unsigned Debug_DEXC_CODE_HI = 14;
- const unsigned Debug_DEXC_CODE_LO = 10;
- const unsigned Debug_NOSST = 9;
- const unsigned Debug_SST = 8;
- const unsigned Debug_OFFLINE = 7;
- const unsigned Debug_DIBIMPR = 6;
- const unsigned Debug_DINT = 5;
- const unsigned Debug_DIB = 4;
- const unsigned Debug_DDBS = 3;
- const unsigned Debug_DDBL = 2;
- const unsigned Debug_DBp = 1;
- const unsigned Debug_DSS = 0;
-
-
- // TraceControl Register - CP0 Reg 23, Sel 1
- const unsigned TraceControl_TS = 31;
- const unsigned TraceControl_UT = 30;
- const unsigned TraceControl_TB = 27;
- const unsigned TraceControl_IO = 26;
- const unsigned TraceControl_D = 25;
- const unsigned TraceControl_E = 24;
- const unsigned TraceControl_K = 23;
- const unsigned TraceControl_S = 22;
- const unsigned TraceControl_U = 21;
- const unsigned TraceControl_ASID_M_HI = 20;
- const unsigned TraceControl_ASID_M_LO = 13;
- const unsigned TraceControl_ASID_HI = 12;
- const unsigned TraceControl_ASID_LO = 5;
- const unsigned TraceControl_G = 4;
- const unsigned TraceControl_TFCR = 3;
- const unsigned TraceControl_TLSM = 2;
- const unsigned TraceControl_TIM = 1;
- const unsigned TraceControl_ON = 0;
-
- // TraceControl2 Register - CP0 Reg 23, Sel 2
- const unsigned TraceControl2_CPUIDV = 29;
- const unsigned TraceControl2_CPUID_HI = 28;
- const unsigned TraceControl2_CPUID_LO = 21;
- const unsigned TraceControl2_TCV = 20;
- const unsigned TraceControl2_TCNUM_HI = 19;
- const unsigned TraceControl2_TCNUM_LO = 12;
- const unsigned TraceControl2_MODE_HI = 11;
- const unsigned TraceControl2_MODE_LO = 7;
- const unsigned TraceControl2_VALIDMODES_HI = 6;
- const unsigned TraceControl2_VALIDMODES_LO = 5;
- const unsigned TraceControl2_TBI = 4;
- const unsigned TraceControl2_TBU = 3;
- const unsigned TraceControl2_SYP_HI = 2;
- const unsigned TraceControl2_SYP_LO = 0;
-
- // UserTraceData Register - CP0 Reg 23, Sel 3
- // Just holds 32-bits (or 64-bits) of data
-
- // TraceIBPC Register - CP0 Reg 23, Sel 4
- const unsigned TraceIBPC_MB = 31;
- const unsigned TraceIBPC_IE = 28;
- const unsigned TraceIBPC_ATE = 27;
- const unsigned TraceIBPC_IBPC8_HI = 26;
- const unsigned TraceIBPC_IBPC8_LO = 24;
- const unsigned TraceIBPC_IBPC7_HI = 23;
- const unsigned TraceIBPC_IBPC7_LO = 21;
- const unsigned TraceIBPC_IBPC6_HI = 20;
- const unsigned TraceIBPC_IBPC6_LO = 18;
- const unsigned TraceIBPC_IBPC5_HI = 17;
- const unsigned TraceIBPC_IBPC5_LO = 15;
- const unsigned TraceIBPC_IBPC4_HI = 14;
- const unsigned TraceIBPC_IBPC4_LO = 12;
- const unsigned TraceIBPC_IBPC3_HI = 11;
- const unsigned TraceIBPC_IBPC3_LO = 9;
- const unsigned TraceIBPC_IBPC2_HI = 8;
- const unsigned TraceIBPC_IBPC2_LO = 6;
- const unsigned TraceIBPC_IBPC1_HI = 5;
- const unsigned TraceIBPC_IBPC1_LO = 3;
- const unsigned TraceIBPC_IBPC0_HI = 2;
- const unsigned TraceIBPC_IBPC0_LO = 0;
-
-
- // TraceDBPC Register - CP0 Reg 23, Sel 5
- const unsigned TRACEDBPC_MB = 31;
- const unsigned TRACEDBPC_DE = 28;
- const unsigned TRACEDBPC_ATE = 27;
- const unsigned TRACEDBPC_DBPC8_HI = 26;
- const unsigned TRACEDBPC_DBPC8_LO = 24;
- const unsigned TRACEDBPC_DBPC7_HI = 23;
- const unsigned TRACEDBPC_DBPC7_LO = 21;
- const unsigned TRACEDBPC_DBPC6_HI = 20;
- const unsigned TRACEDBPC_DBPC6_LO = 18;
- const unsigned TRACEDBPC_DBPC5_HI = 17;
- const unsigned TRACEDBPC_DBPC5_LO = 15;
- const unsigned TRACEDBPC_DBPC4_HI = 14;
- const unsigned TRACEDBPC_DBPC4_LO = 12;
- const unsigned TRACEDBPC_DBPC3_HI = 11;
- const unsigned TRACEDBPC_DBPC3_LO = 9;
- const unsigned TRACEDBPC_DBPC2_HI = 8;
- const unsigned TRACEDBPC_DBPC2_LO = 6;
- const unsigned TRACEDBPC_DBPC1_HI = 5;
- const unsigned TRACEDBPC_DBPC1_LO = 3;
- const unsigned TRACEDBPC_DBPC0_HI = 2;
- const unsigned TRACEDBPC_DBPC0_LO = 0;
-
- // TraceIBPC2 - Not part of CP0, but part of TRACE
- const unsigned TraceIBPC_IBPC14_HI = 17;
- const unsigned TraceIBPC_IBPC14_LO = 15;
- const unsigned TraceIBPC_IBPC13_HI = 14;
- const unsigned TraceIBPC_IBPC13_LO = 12;
- const unsigned TraceIBPC_IBPC12_HI = 11;
- const unsigned TraceIBPC_IBPC12_LO = 9;
- const unsigned TraceIBPC_IBPC11_HI = 8;
- const unsigned TraceIBPC_IBPC11_LO = 6;
- const unsigned TraceIBPC_IBPC10_HI = 5;
- const unsigned TraceIBPC_IBPC10_LO = 3;
- const unsigned TraceIBPC_IBPC9_HI = 2;
- const unsigned TraceIBPC_IBPC9_LO = 0;
-
-
- // TraceDBPC2 - Not part of CP0, but part of TRACE
- const unsigned TRACEDBPC_DBPC14_HI = 17;
- const unsigned TRACEDBPC_DBPC14_LO = 15;
- const unsigned TRACEDBPC_DBPC13_HI = 14;
- const unsigned TRACEDBPC_DBPC13_LO = 12;
- const unsigned TRACEDBPC_DBPC12_HI = 11;
- const unsigned TRACEDBPC_DBPC12_LO = 9;
- const unsigned TRACEDBPC_DBPC11_HI = 8;
- const unsigned TRACEDBPC_DBPC11_LO = 6;
- const unsigned TRACEDBPC_DBPC10_HI = 5;
- const unsigned TRACEDBPC_DBPC10_LO = 3;
- const unsigned TRACEDBPC_DBPC9_HI = 2;
- const unsigned TRACEDBPC_DBPC9_LO = 0;
-
-
- // Debug Register 2 - CP0 Reg 23, Sel 6
- const unsigned DEBUG2_PRM = 3;
- const unsigned DEBUG2_DQ = 2;
- const unsigned DEBUG2_TUP = 1;
- const unsigned DEBUG2_PACO = 0;
-
- // DEPC Register - CP0 Reg 24, Sel 0
- // Debug Exception Program Counter
- const unsigned DEPC_HI = 31;
- const unsigned DEPC_LO = 0;
-
-
-
- // DESAVE - CP0 Reg 31, Sel 0
- // Debug Exception Save Register
- const unsigned DESAVE_HI = 31;
- const unsigned DESAVE_LO = 0;
-
-
+BitUnion32(DebugReg)
+ Bitfield<31> dbd;
+ Bitfield<30> dm;
+ Bitfield<29> nodcr;
+ Bitfield<28> lsnm;
+ Bitfield<27> doze;
+ Bitfield<26> halt;
+ Bitfield<25> conutdm;
+ Bitfield<24> ibusep;
+ Bitfield<23> mcheckep;
+ Bitfield<22> cacheep;
+ Bitfield<21> dbusep;
+ Bitfield<20, 19> iexi;
+ Bitfield<19> ddbsImpr;
+ Bitfield<18> ddblImpr;
+ SubBitUnion(ejtagVer, 17, 15)
+ Bitfield<17> ejtagVer2;
+ Bitfield<16> ejtagVer1;
+ Bitfield<15> ejtagVer0;
+ EndSubBitUnion(ejtagVer)
+ Bitfield<14, 10> dexcCode;
+ Bitfield<9> nosst;
+ Bitfield<8> sst;
+ Bitfield<7> offline;
+ Bitfield<6> dibimpr;
+ Bitfield<5> dint;
+ Bitfield<4> dib;
+ Bitfield<3> ddbs;
+ Bitfield<2> ddbl;
+ Bitfield<1> dbp;
+ Bitfield<0> dss;
+EndBitUnion(DebugReg)
+
+BitUnion32(TraceControlReg)
+ Bitfield<31> ts;
+ Bitfield<30> ut;
+ Bitfield<27> tb;
+ Bitfield<26> io;
+ Bitfield<25> d;
+ Bitfield<24> e;
+ Bitfield<23> k;
+ Bitfield<22> s;
+ Bitfield<21> u;
+ Bitfield<20, 13> asidM;
+ Bitfield<12, 5> asid;
+ Bitfield<4> g;
+ Bitfield<3> tfcr;
+ Bitfield<2> tlsm;
+ Bitfield<1> tim;
+ Bitfield<0> on;
+EndBitUnion(TraceControlReg)
+
+BitUnion32(TraceControl2Reg)
+ Bitfield<29> cpuidv;
+ Bitfield<28, 21> cpuid;
+ Bitfield<20> tcv;
+ Bitfield<19, 12> tcnum;
+ Bitfield<11, 7> mode;
+ Bitfield<6, 5> validModes;
+ Bitfield<4> tbi;
+ Bitfield<3> tbu;
+ Bitfield<2, 0> syp;
+EndBitUnion(TraceControl2Reg)
+
+BitUnion32(TraceBPCReg)
+ Bitfield<31> mb;
+ Bitfield<28> e;
+ Bitfield<27> ate;
+ Bitfield<26, 24> bpc8;
+ Bitfield<23, 21> bpc7;
+ Bitfield<20, 18> bpc6;
+ Bitfield<17, 15> bpc5;
+ Bitfield<14, 12> bpc4;
+ Bitfield<11, 9> bpc3;
+ Bitfield<8, 6> bpc2;
+ Bitfield<5, 3> bpc1;
+ Bitfield<2, 0> bpc0;
+EndBitUnion(TraceBPCReg)
+
+BitUnion32(TraceBPC2Reg)
+ Bitfield<17, 15> bpc14;
+ Bitfield<14, 12> bpc13;
+ Bitfield<11, 9> bpc12;
+ Bitfield<8, 6> bpc11;
+ Bitfield<5, 3> bpc10;
+ Bitfield<2, 0> bpc9;
+EndBitUnion(TraceBPC2Reg)
+
+BitUnion32(Debug2Reg)
+ Bitfield<3> prm;
+ Bitfield<2> dq;
+ Bitfield<1> tup;
+ Bitfield<0> paco;
+EndBitUnion(Debug2Reg)
} // namespace MipsISA
#endif
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index f03a72e98..a3538435c 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -110,8 +110,8 @@ ISA::init()
miscRegFile_WriteMask.resize(NumMiscRegs);
- for (int i=0; i < NumMiscRegs; i++) {
- miscRegFile_WriteMask[i].push_back(0);
+ for (int i = 0; i < NumMiscRegs; i++) {
+ miscRegFile_WriteMask[i].push_back(0);
}
clear(0);
}
@@ -181,253 +181,244 @@ ISA::reset(std::string core_name, ThreadID num_threads,
// ===================================================
DPRINTF(MipsPRA, "Initializing CP0 State.... ");
- MiscReg ProcID = readMiscRegNoEffect(PRId);
- replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions);
- replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID);
- replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID);
- replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision);
- setMiscRegNoEffect(PRId,ProcID);
+ PRIdReg procId = readMiscRegNoEffect(PRId);
+ procId.coOp = cp.CP0_PRId_CompanyOptions;
+ procId.coId = cp.CP0_PRId_CompanyID;
+ procId.procId = cp.CP0_PRId_ProcessorID;
+ procId.rev = cp.CP0_PRId_Revision;
+ setMiscRegNoEffect(PRId, procId);
+
// Now, create Write Mask for ProcID register
MiscReg ProcID_Mask = 0; // Read-Only register
- replaceBits(ProcID_Mask,0,32,0);
- setRegMask(PRId,ProcID_Mask);
+ replaceBits(ProcID_Mask, 0, 32, 0);
+ setRegMask(PRId, ProcID_Mask);
// Config
- MiscReg cfg = readMiscRegNoEffect(Config);
- replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE);
- replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT);
- replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR);
- replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT);
- replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI);
- replaceBits(cfg, Config_M, 1);
+ ConfigReg cfg = readMiscRegNoEffect(Config);
+ cfg.be = cp.CP0_Config_BE;
+ cfg.at = cp.CP0_Config_AT;
+ cfg.ar = cp.CP0_Config_AR;
+ cfg.mt = cp.CP0_Config_MT;
+ cfg.vi = cp.CP0_Config_VI;
+ cfg.m = 1;
setMiscRegNoEffect(Config, cfg);
// Now, create Write Mask for Config register
MiscReg cfg_Mask = 0x7FFF0007;
- replaceBits(cfg_Mask,0,32,0);
- setRegMask(Config,cfg_Mask);
+ replaceBits(cfg_Mask, 0, 32, 0);
+ setRegMask(Config, cfg_Mask);
// Config1
- MiscReg cfg1 = readMiscRegNoEffect(Config1);
- replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO,
- cp.CP0_Config1_MMU);
- replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS);
- replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL);
- replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA);
- replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, cp.CP0_Config1_DS);
- replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, cp.CP0_Config1_DL);
- replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, cp.CP0_Config1_DA);
- replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, cp.CP0_Config1_FP);
- replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, cp.CP0_Config1_EP);
- replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, cp.CP0_Config1_WR);
- replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, cp.CP0_Config1_MD);
- replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2);
- replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC);
- replaceBits(cfg1, Config1_M, cp.CP0_Config1_M);
+ Config1Reg cfg1 = readMiscRegNoEffect(Config1);
+ cfg1.mmuSize = cp.CP0_Config1_MMU;
+ cfg1.is = cp.CP0_Config1_IS;
+ cfg1.il = cp.CP0_Config1_IL;
+ cfg1.ia = cp.CP0_Config1_IA;
+ cfg1.ds = cp.CP0_Config1_DS;
+ cfg1.dl = cp.CP0_Config1_DL;
+ cfg1.da = cp.CP0_Config1_DA;
+ cfg1.fp = cp.CP0_Config1_FP;
+ cfg1.ep = cp.CP0_Config1_EP;
+ cfg1.wr = cp.CP0_Config1_WR;
+ cfg1.md = cp.CP0_Config1_MD;
+ cfg1.c2 = cp.CP0_Config1_C2;
+ cfg1.pc = cp.CP0_Config1_PC;
+ cfg1.m = cp.CP0_Config1_M;
setMiscRegNoEffect(Config1, cfg1);
// Now, create Write Mask for Config register
MiscReg cfg1_Mask = 0; // Read Only Register
- replaceBits(cfg1_Mask,0,32,0);
- setRegMask(Config1,cfg1_Mask);
+ replaceBits(cfg1_Mask, 0, 32, 0);
+ setRegMask(Config1, cfg1_Mask);
// Config2
- MiscReg cfg2 = readMiscRegNoEffect(Config2);
- replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU);
- replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS);
- replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL);
- replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, cp.CP0_Config2_TA);
- replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, cp.CP0_Config2_SU);
- replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, cp.CP0_Config2_SS);
- replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL);
- replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA);
- replaceBits(cfg2, Config2_M, cp.CP0_Config2_M);
+ Config2Reg cfg2 = readMiscRegNoEffect(Config2);
+ cfg2.tu = cp.CP0_Config2_TU;
+ cfg2.ts = cp.CP0_Config2_TS;
+ cfg2.tl = cp.CP0_Config2_TL;
+ cfg2.ta = cp.CP0_Config2_TA;
+ cfg2.su = cp.CP0_Config2_SU;
+ cfg2.ss = cp.CP0_Config2_SS;
+ cfg2.sl = cp.CP0_Config2_SL;
+ cfg2.sa = cp.CP0_Config2_SA;
+ cfg2.m = cp.CP0_Config2_M;
setMiscRegNoEffect(Config2, cfg2);
// Now, create Write Mask for Config register
MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
- replaceBits(cfg2_Mask,0,32,0);
- setRegMask(Config2,cfg2_Mask);
+ replaceBits(cfg2_Mask, 0, 32, 0);
+ setRegMask(Config2, cfg2_Mask);
// Config3
- MiscReg cfg3 = readMiscRegNoEffect(Config3);
- replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP);
- replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA);
- replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC);
- replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, cp.CP0_Config3_VInt);
- replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, cp.CP0_Config3_SP);
- replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT);
- replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM);
- replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL);
+ Config3Reg cfg3 = readMiscRegNoEffect(Config3);
+ cfg3.dspp = cp.CP0_Config3_DSPP;
+ cfg3.lpa = cp.CP0_Config3_LPA;
+ cfg3.veic = cp.CP0_Config3_VEIC;
+ cfg3.vint = cp.CP0_Config3_VInt;
+ cfg3.sp = cp.CP0_Config3_SP;
+ cfg3.mt = cp.CP0_Config3_MT;
+ cfg3.sm = cp.CP0_Config3_SM;
+ cfg3.tl = cp.CP0_Config3_TL;
setMiscRegNoEffect(Config3, cfg3);
// Now, create Write Mask for Config register
MiscReg cfg3_Mask = 0; // Read Only Register
- replaceBits(cfg3_Mask,0,32,0);
- setRegMask(Config3,cfg3_Mask);
+ replaceBits(cfg3_Mask, 0, 32, 0);
+ setRegMask(Config3, cfg3_Mask);
// EBase - CPUNum
- MiscReg EB = readMiscRegNoEffect(EBase);
- replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum);
- replaceBits(EB, 31, 31, 1);
- setMiscRegNoEffect(EBase, EB);
+ EBaseReg eBase = readMiscRegNoEffect(EBase);
+ eBase.cpuNum = cp.CP0_EBase_CPUNum;
+ replaceBits(eBase, 31, 31, 1);
+ setMiscRegNoEffect(EBase, eBase);
// Now, create Write Mask for Config register
MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
// entire register is read only
- replaceBits(EB_Mask,0,32,0);
- setRegMask(EBase,EB_Mask);
+ replaceBits(EB_Mask, 0, 32, 0);
+ setRegMask(EBase, EB_Mask);
// SRS Control - HSS (Highest Shadow Set)
- MiscReg SC = readMiscRegNoEffect(SRSCtl);
- replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS);
- setMiscRegNoEffect(SRSCtl, SC);
+ SRSCtlReg scsCtl = readMiscRegNoEffect(SRSCtl);
+ scsCtl.hss = cp.CP0_SrsCtl_HSS;
+ setMiscRegNoEffect(SRSCtl, scsCtl);
// Now, create Write Mask for the SRS Ctl register
MiscReg SC_Mask = 0x0000F3C0;
- replaceBits(SC_Mask,0,32,0);
- setRegMask(SRSCtl,SC_Mask);
+ replaceBits(SC_Mask, 0, 32, 0);
+ setRegMask(SRSCtl, SC_Mask);
// IntCtl - IPTI, IPPCI
- MiscReg IC = readMiscRegNoEffect(IntCtl);
- replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI);
- replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI);
- setMiscRegNoEffect(IntCtl, IC);
+ IntCtlReg intCtl = readMiscRegNoEffect(IntCtl);
+ intCtl.ipti = cp.CP0_IntCtl_IPTI;
+ intCtl.ippci = cp.CP0_IntCtl_IPPCI;
+ setMiscRegNoEffect(IntCtl, intCtl);
// Now, create Write Mask for the IntCtl register
MiscReg IC_Mask = 0x000003E0;
- replaceBits(IC_Mask,0,32,0);
- setRegMask(IntCtl,IC_Mask);
+ replaceBits(IC_Mask, 0, 32, 0);
+ setRegMask(IntCtl, IC_Mask);
// Watch Hi - M - FIXME (More than 1 Watch register)
- MiscReg WHi = readMiscRegNoEffect(WatchHi0);
- replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M);
- setMiscRegNoEffect(WatchHi0, WHi);
+ WatchHiReg watchHi = readMiscRegNoEffect(WatchHi0);
+ watchHi.m = cp.CP0_WatchHi_M;
+ setMiscRegNoEffect(WatchHi0, watchHi);
// Now, create Write Mask for the IntCtl register
MiscReg wh_Mask = 0x7FFF0FFF;
- replaceBits(wh_Mask,0,32,0);
- setRegMask(WatchHi0,wh_Mask);
+ replaceBits(wh_Mask, 0, 32, 0);
+ setRegMask(WatchHi0, wh_Mask);
// Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
- MiscReg PCtr = readMiscRegNoEffect(PerfCnt0);
- replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M);
- replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W);
- setMiscRegNoEffect(PerfCnt0, PCtr);
+ PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(PerfCnt0);
+ perfCntCtl.m = cp.CP0_PerfCtr_M;
+ perfCntCtl.w = cp.CP0_PerfCtr_W;
+ setMiscRegNoEffect(PerfCnt0, perfCntCtl);
// Now, create Write Mask for the IntCtl register
MiscReg pc_Mask = 0x00007FF;
- replaceBits(pc_Mask,0,32,0);
- setRegMask(PerfCnt0,pc_Mask);
+ replaceBits(pc_Mask, 0, 32, 0);
+ setRegMask(PerfCnt0, pc_Mask);
// Random
- MiscReg random = readMiscRegNoEffect(CP0_Random);
- random = 63;
- setMiscRegNoEffect(CP0_Random, random);
+ setMiscRegNoEffect(CP0_Random, 63);
// Now, create Write Mask for the IntCtl register
MiscReg random_Mask = 0;
- replaceBits(random_Mask,0,32,0);
- setRegMask(CP0_Random,random_Mask);
+ replaceBits(random_Mask, 0, 32, 0);
+ setRegMask(CP0_Random, random_Mask);
// PageGrain
- MiscReg pagegrain = readMiscRegNoEffect(PageGrain);
- replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP);
- setMiscRegNoEffect(PageGrain, pagegrain);
+ PageGrainReg pageGrain = readMiscRegNoEffect(PageGrain);
+ pageGrain.esp = cp.CP0_Config3_SP;
+ setMiscRegNoEffect(PageGrain, pageGrain);
// Now, create Write Mask for the IntCtl register
MiscReg pg_Mask = 0x10000000;
- replaceBits(pg_Mask,0,32,0);
- setRegMask(PageGrain,pg_Mask);
+ replaceBits(pg_Mask, 0, 32, 0);
+ setRegMask(PageGrain, pg_Mask);
// Status
- MiscReg stat = readMiscRegNoEffect(Status);
+ StatusReg status = readMiscRegNoEffect(Status);
// Only CU0 and IE are modified on a reset - everything else needs
// to be controlled on a per CPU model basis
// Enable CP0 on reset
- // replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1);
+ // status.cu0 = 1;
// Enable ERL bit on a reset
- replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1);
-
+ status.erl = 1;
// Enable BEV bit on a reset
- replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1);
+ status.bev = 1;
- setMiscRegNoEffect(Status, stat);
+ setMiscRegNoEffect(Status, status);
// Now, create Write Mask for the Status register
MiscReg stat_Mask = 0xFF78FF17;
- replaceBits(stat_Mask,0,32,0);
- setRegMask(Status,stat_Mask);
+ replaceBits(stat_Mask, 0, 32, 0);
+ setRegMask(Status, stat_Mask);
// MVPConf0
- MiscReg mvp_conf0 = readMiscRegNoEffect(MVPConf0);
- replaceBits(mvp_conf0, MVPC0_TCA, 1);
- replaceBits(mvp_conf0, MVPC0_PVPE_HI, MVPC0_PVPE_LO, num_vpes - 1);
- replaceBits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO, num_threads - 1);
- setMiscRegNoEffect(MVPConf0, mvp_conf0);
+ MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
+ mvpConf0.tca = 1;
+ mvpConf0.pvpe = num_vpes - 1;
+ mvpConf0.ptc = num_threads - 1;
+ setMiscRegNoEffect(MVPConf0, mvpConf0);
// VPEConf0
- MiscReg vpe_conf0 = readMiscRegNoEffect(VPEConf0);
- replaceBits(vpe_conf0, VPEC0_MVP, 1);
- setMiscRegNoEffect(VPEConf0, vpe_conf0);
+ VPEConf0Reg vpeConf0 = readMiscRegNoEffect(VPEConf0);
+ vpeConf0.mvp = 1;
+ setMiscRegNoEffect(VPEConf0, vpeConf0);
// TCBind
for (ThreadID tid = 0; tid < num_threads; tid++) {
- MiscReg tc_bind = readMiscRegNoEffect(TCBind, tid);
- replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
- setMiscRegNoEffect(TCBind, tc_bind, tid);
+ TCBindReg tcBind = readMiscRegNoEffect(TCBind, tid);
+ tcBind.curTC = tid;
+ setMiscRegNoEffect(TCBind, tcBind, tid);
}
// TCHalt
- MiscReg tc_halt = readMiscRegNoEffect(TCHalt);
- replaceBits(tc_halt, TCH_H, 0);
- setMiscRegNoEffect(TCHalt, tc_halt);
- /*for (ThreadID tid = 1; tid < num_threads; tid++) {
- // Set TCHalt Halt bit to 1 for all other threads
- tc_halt = readMiscRegNoEffect(TCHalt, tid);
- replaceBits(tc_halt, TCH_H, 1);
- setReg(TCHalt, tc_halt, tid);
- }*/
+ TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt);
+ tcHalt.h = 0;
+ setMiscRegNoEffect(TCHalt, tcHalt);
// TCStatus
// Set TCStatus Activated to 1 for the initial thread that is running
- MiscReg tc_status = readMiscRegNoEffect(TCStatus);
- replaceBits(tc_status, TCS_A, 1);
- setMiscRegNoEffect(TCStatus, tc_status);
+ TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus);
+ tcStatus.a = 1;
+ setMiscRegNoEffect(TCStatus, tcStatus);
// Set Dynamically Allocatable bit to 1 for all other threads
for (ThreadID tid = 1; tid < num_threads; tid++) {
- tc_status = readMiscRegNoEffect(TCStatus, tid);
- replaceBits(tc_status, TCSTATUS_DA, 1);
- setMiscRegNoEffect(TCStatus, tc_status, tid);
+ tcStatus = readMiscRegNoEffect(TCStatus, tid);
+ tcStatus.da = 1;
+ setMiscRegNoEffect(TCStatus, tcStatus, tid);
}
MiscReg Mask = 0x7FFFFFFF;
// Now, create Write Mask for the Index register
- replaceBits(Mask,0,32,0);
- setRegMask(Index,Mask);
+ replaceBits(Mask, 0, 32, 0);
+ setRegMask(Index, Mask);
Mask = 0x3FFFFFFF;
- replaceBits(Mask,0,32,0);
- setRegMask(EntryLo0,Mask);
- setRegMask(EntryLo1,Mask);
+ replaceBits(Mask, 0, 32, 0);
+ setRegMask(EntryLo0, Mask);
+ setRegMask(EntryLo1, Mask);
Mask = 0xFF800000;
- replaceBits(Mask,0,32,0);
- setRegMask(Context,Mask);
+ replaceBits(Mask, 0, 32, 0);
+ setRegMask(Context, Mask);
Mask = 0x1FFFF800;
- replaceBits(Mask,0,32,0);
- setRegMask(PageMask,Mask);
+ replaceBits(Mask, 0, 32, 0);
+ setRegMask(PageMask, Mask);
Mask = 0x0;
- replaceBits(Mask,0,32,0);
- setRegMask(BadVAddr,Mask);
- setRegMask(LLAddr,Mask);
+ replaceBits(Mask, 0, 32, 0);
+ setRegMask(BadVAddr, Mask);
+ setRegMask(LLAddr, Mask);
Mask = 0x08C00300;
- replaceBits(Mask,0,32,0);
- setRegMask(Cause,Mask);
+ replaceBits(Mask, 0, 32, 0);
+ setRegMask(Cause, Mask);
}
inline unsigned
ISA::getVPENum(ThreadID tid)
{
- unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
- return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
+ TCBindReg tcBind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
+ return tcBind.curVPE;
}
MiscReg
@@ -561,22 +552,22 @@ ISA::updateCPU()
// EVALUATE CP0 STATE FOR MIPS MT
//
///////////////////////////////////////////////////////////////////
- unsigned mvp_conf0 = readMiscRegNoEffect(MVPConf0);
- ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
+ MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
+ ThreadID num_threads = mvpConf0.ptc + 1;
for (ThreadID tid = 0; tid < num_threads; tid++) {
- MiscReg tc_status = readMiscRegNoEffect(TCStatus, tid);
- MiscReg tc_halt = readMiscRegNoEffect(TCHalt, tid);
+ TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus, tid);
+ TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt, tid);
//@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
- if (bits(tc_halt, TCH_H) == 1 || bits(tc_status, TCS_A) == 0) {
+ if (tcHalt.h == 1 || tcStatus.a == 0) {
haltThread(cpu->getContext(tid));
- } else if (bits(tc_halt, TCH_H) == 0 && bits(tc_status, TCS_A) == 1) {
+ } else if (tcHalt.h == 0 && tcStatus.a == 1) {
restoreThread(cpu->getContext(tid));
}
}
- num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
+ num_threads = mvpConf0.ptc + 1;
// Toggle update flag after we finished updating
cp0Updated = false;
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index a463093ec..7a6d5db05 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -120,8 +120,22 @@ decode OPCODE_HI default Unknown::unknown() {
//used to distinguish JR from JR.HB and JALR from JALR.HB"
format Jump {
0x0: decode HINT {
- 0x1: jr_hb({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");}; }}, IsReturn, ClearHazards);
- default: jr({{ if(Config1_CA == 0){NNPC = Rs;}else{panic("MIPS16e not supported\n");};}}, IsReturn);
+ 0x1: jr_hb({{
+ Config1Reg config1 = Config1;
+ if (config1.ca == 0) {
+ NNPC = Rs;
+ } else {
+ panic("MIPS16e not supported\n");
+ }
+ }}, IsReturn, ClearHazards);
+ default: jr({{
+ Config1Reg config1 = Config1;
+ if (config1.ca == 0) {
+ NNPC = Rs;
+ } else {
+ panic("MIPS16e not supported\n");
+ }
+ }}, IsReturn);
}
0x1: decode HINT {
@@ -351,25 +365,32 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode RS_MSB {
0x0: decode RS {
format CP0Control {
- 0x0: mfc0({{ Rt = CP0_RD_SEL;
- /* Hack for PageMask */
- if(RD == 5) // PageMask
- if(Config3_SP == 0 || PageGrain_ESP == 0)
- Rt &= 0xFFFFE7FF;
- }});
- 0x4: mtc0({{ CP0_RD_SEL = Rt;
-
- if(RD == 11) // Compare{
- if(Cause_TI == 1){
- Cause_TI = 0;
- MiscReg cause = xc->readMiscRegNoEffect(MipsISA::Cause);
- int Offset = 10; // corresponding to Cause_IP0
- Offset += ((IntCtl_IPTI) - 2);
- replaceBits(cause,Offset,Offset,0);
- xc->setMiscRegNoEffect(MipsISA::Cause,cause);
- }
-
- }});
+ 0x0: mfc0({{
+ Config3Reg config3 = Config3;
+ PageGrainReg pageGrain = PageGrain;
+ Rt = CP0_RD_SEL;
+ /* Hack for PageMask */
+ if (RD == 5) {
+ // PageMask
+ if(config3.sp == 0 || pageGrain.esp == 0)
+ Rt &= 0xFFFFE7FF;
+ }
+ }});
+ 0x4: mtc0({{
+ CP0_RD_SEL = Rt;
+ CauseReg cause = Cause;
+ IntCtlReg intCtl = IntCtl;
+ if (RD == 11) {
+ // Compare
+ if (cause.ti == 1) {
+ cause.ti = 0;
+ int offset = 10; // corresponding to cause.ip0
+ offset += intCtl.ipti - 2;
+ replaceBits(cause, offset, offset, 0);
+ }
+ }
+ Cause = cause;
+ }});
}
format CP0Unimpl {
0x1: dmfc0();
@@ -378,9 +399,10 @@ decode OPCODE_HI default Unknown::unknown() {
}
format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
0x8: decode MT_U {
- 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
- Ctrl_Base_DepTag);
- }});
+ 0x0: mftc0({{
+ data = xc->readRegOtherThread((RT << 3 | SEL) +
+ Ctrl_Base_DepTag);
+ }});
0x1: decode SEL {
0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
0x1: decode RT {
@@ -537,16 +559,22 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: decode POS {
0x0: decode SEL {
0x1: decode SC {
- 0x0: dvpe({{ Rt = MVPControl;
- if (VPEConf0<VPEC0_MVP:> == 1) {
- MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
- }
- }});
- 0x1: evpe({{ Rt = MVPControl;
- if (VPEConf0<VPEC0_MVP:> == 1) {
- MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
- }
- }});
+ 0x0: dvpe({{
+ MVPControlReg mvpControl = MVPControl;
+ VPEConf0Reg vpeConf0 = VPEConf0;
+ Rt = MVPControl;
+ if (vpeConf0.mvp == 1)
+ mvpControl.evp = 0;
+ MVPControl = mvpControl;
+ }});
+ 0x1: evpe({{
+ MVPControlReg mvpControl = MVPControl;
+ VPEConf0Reg vpeConf0 = VPEConf0;
+ Rt = MVPControl;
+ if (vpeConf0.mvp == 1)
+ mvpControl.evp = 1;
+ MVPControl = mvpControl;
+ }});
default:CP0Unimpl::unknown();
}
default:CP0Unimpl::unknown();
@@ -557,12 +585,18 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode POS {
0xF: decode SEL {
0x1: decode SC {
- 0x0: dmt({{ Rt = VPEControl;
- VPEControl = insertBits(VPEControl, VPEC_TE, 0);
- }});
- 0x1: emt({{ Rt = VPEControl;
- VPEControl = insertBits(VPEControl, VPEC_TE, 1);
- }});
+ 0x0: dmt({{
+ VPEControlReg vpeControl = VPEControl;
+ Rt = vpeControl;
+ vpeControl.te = 0;
+ VPEControl = vpeControl;
+ }});
+ 0x1: emt({{
+ VPEControlReg vpeControl = VPEControl;
+ Rt = vpeControl;
+ vpeControl.te = 1;
+ VPEControl = vpeControl;
+ }});
default:CP0Unimpl::unknown();
}
default:CP0Unimpl::unknown();
@@ -573,27 +607,29 @@ decode OPCODE_HI default Unknown::unknown() {
0xC: decode POS {
0x0: decode SC {
0x0: CP0Control::di({{
- if(Config_AR >= 1) // Rev 2.0 or beyond?
- {
- Rt = Status;
- Status_IE = 0;
- }
- else // Enable this else branch once we actually set values for Config on init
- {
+ StatusReg status = Status;
+ ConfigReg config = Config;
+ // Rev 2.0 or beyond?
+ if (config.ar >= 1) {
+ Rt = status;
+ status.ie = 0;
+ } else {
+ // Enable this else branch once we
+ // actually set values for Config on init
fault = new ReservedInstructionFault();
- }
- }});
+ }
+ Status = status;
+ }});
0x1: CP0Control::ei({{
- if(Config_AR >= 1)
- {
- Rt = Status;
- Status_IE = 1;
- }
- else
- {
+ StatusReg status = Status;
+ ConfigReg config = Config;
+ if (config.ar >= 1) {
+ Rt = status;
+ status.ie = 1;
+ } else {
fault = new ReservedInstructionFault();
- }
- }});
+ }
+ }});
default:CP0Unimpl::unknown();
}
}
@@ -601,29 +637,23 @@ decode OPCODE_HI default Unknown::unknown() {
}
format CP0Control {
0xA: rdpgpr({{
- if(Config_AR >= 1)
- { // Rev 2 of the architecture
- panic("Shadow Sets Not Fully Implemented.\n");
- //Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS);
- }
- else
- {
+ ConfigReg config = Config;
+ if (config.ar >= 1) {
+ // Rev 2 of the architecture
+ panic("Shadow Sets Not Fully Implemented.\n");
+ } else {
fault = new ReservedInstructionFault();
}
- }});
+ }});
0xE: wrpgpr({{
- if(Config_AR >= 1)
- { // Rev 2 of the architecture
- panic("Shadow Sets Not Fully Implemented.\n");
- //xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt);
- // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl);
+ ConfigReg config = Config;
+ if (config.ar >= 1) {
+ // Rev 2 of the architecture
+ panic("Shadow Sets Not Fully Implemented.\n");
+ } else {
+ fault = new ReservedInstructionFault();
}
- else
- {
- fault = new ReservedInstructionFault();
- }
-
- }});
+ }});
}
}
@@ -632,44 +662,43 @@ decode OPCODE_HI default Unknown::unknown() {
0x1: decode FUNCTION {
format CP0Control {
0x18: eret({{
- DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
- // Ugly hack to get the value of Status_EXL
- if(Status_EXL == 1){
- DPRINTF(MipsPRA,"ERET EXL Hack\n");
- }
- if(Status_ERL == 1){
- Status_ERL = 0;
- NPC = ErrorEPC;
- NNPC = ErrorEPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
- }
- else {
- NPC = EPC;
- NNPC = EPC + sizeof(MachInst); // Need to adjust NNPC, otherwise things break
- Status_EXL = 0;
- if(Config_AR >=1 && SRSCtl_HSS > 0 && Status_BEV == 0){
- SRSCtl_CSS = SRSCtl_PSS;
- //xc->setShadowSet(SRSCtl_PSS);
+ StatusReg status = Status;
+ ConfigReg config = Config;
+ SRSCtlReg srsCtl = SRSCtl;
+ DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC);
+ if (status.erl == 1) {
+ status.erl = 0;
+ NPC = ErrorEPC;
+ // Need to adjust NNPC, otherwise things break
+ NNPC = ErrorEPC + sizeof(MachInst);
+ } else {
+ NPC = EPC;
+ // Need to adjust NNPC, otherwise things break
+ NNPC = EPC + sizeof(MachInst);
+ status.exl = 0;
+ if (config.ar >=1 &&
+ srsCtl.hss > 0 &&
+ status.bev == 0) {
+ srsCtl.css = srsCtl.pss;
+ //xc->setShadowSet(srsCtl.pss);
+ }
}
- }
- LLFlag = 0;
- }},IsReturn,IsSerializing,IsERET);
+ LLFlag = 0;
+ Status = status;
+ SRSCtl = srsCtl;
+ }},IsReturn,IsSerializing,IsERET);
0x1F: deret({{
- // if(EJTagImplemented()) {
- if(Debug_DM == 1){
- Debug_DM = 1;
- Debug_IEXI = 0;
- NPC = DEPC;
- }
- else
- {
- // Undefined;
- }
- //} // EJTag Implemented
- //else {
- // Reserved Instruction Exception
- //}
- }},IsReturn,IsSerializing,IsERET);
+ DebugReg debug = Debug;
+ if (debug.dm == 1) {
+ debug.dm = 1;
+ debug.iexi = 0;
+ NPC = DEPC;
+ } else {
+ // Undefined;
+ }
+ Debug = debug;
+ }}, IsReturn, IsSerializing, IsERET);
}
format CP0TLB {
0x01: tlbr({{
@@ -689,140 +718,157 @@ decode OPCODE_HI default Unknown::unknown() {
}}); // Need to hook up to TLB
0x02: tlbwi({{
- //Create PTE
- MipsISA::PTE NewEntry;
- //Write PTE
- NewEntry.Mask = (Addr)(PageMask >> 11);
- NewEntry.VPN = (Addr)(EntryHi >> 11);
- /* PageGrain _ ESP Config3 _ SP */
- if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
- NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
- NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
- }
- NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
-
- NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
- NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
- NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
- NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
- NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
- NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
- NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
- NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
- NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
- /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
- /* Addr Shift Amount for 1KB or larger pages */
- // warn("PTE->Mask: %x\n",pte->Mask);
- if((NewEntry.Mask & 0xFFFF) == 3){
- NewEntry.AddrShiftAmount = 12;
- } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
- NewEntry.AddrShiftAmount = 10;
- } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
- NewEntry.AddrShiftAmount = 14;
- } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
- NewEntry.AddrShiftAmount = 16;
- } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
- NewEntry.AddrShiftAmount = 18;
- } else if((NewEntry.Mask & 0xFF00) == 0x0300){
- NewEntry.AddrShiftAmount = 20;
- } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
- NewEntry.AddrShiftAmount = 22;
- } else if((NewEntry.Mask & 0xF000) == 0x3000){
- NewEntry.AddrShiftAmount = 24;
- } else if((NewEntry.Mask & 0xC000) == 0xC000){
- NewEntry.AddrShiftAmount = 26;
- } else if((NewEntry.Mask & 0x30000) == 0x30000){
- NewEntry.AddrShiftAmount = 28;
- } else {
- fatal("Invalid Mask Pattern Detected!\n");
- }
- NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
-
- MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
- MiscReg c3=xc->readMiscReg(MipsISA::Config3);
- MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
- int SP=0;
- if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
- SP=1;
- }
- Ptr->insertAt(NewEntry,Index & 0x7FFFFFFF,SP);
+ //Create PTE
+ MipsISA::PTE NewEntry;
+ //Write PTE
+ NewEntry.Mask = (Addr)(PageMask >> 11);
+ NewEntry.VPN = (Addr)(EntryHi >> 11);
+ /* PageGrain _ ESP Config3 _ SP */
+ if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
+ // If 1KB pages are *NOT* enabled, lowest bits of the
+ // mask are 0b11 for TLB writes
+ NewEntry.Mask |= 0x3;
+ // Reset bits 0 and 1 if 1KB pages are not enabled
+ NewEntry.VPN &= 0xFFFFFFFC;
+ }
+ NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
+
+ NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
+ NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
+ NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
+ NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
+ NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
+ NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
+ NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
+ NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
+ NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
+ /* Now, compute the AddrShiftAmount and OffsetMask - TLB
+ optimizations */
+ /* Addr Shift Amount for 1KB or larger pages */
+ if ((NewEntry.Mask & 0xFFFF) == 3) {
+ NewEntry.AddrShiftAmount = 12;
+ } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) {
+ NewEntry.AddrShiftAmount = 10;
+ } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) {
+ NewEntry.AddrShiftAmount = 14;
+ } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) {
+ NewEntry.AddrShiftAmount = 16;
+ } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) {
+ NewEntry.AddrShiftAmount = 18;
+ } else if ((NewEntry.Mask & 0xFF00) == 0x0300) {
+ NewEntry.AddrShiftAmount = 20;
+ } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) {
+ NewEntry.AddrShiftAmount = 22;
+ } else if ((NewEntry.Mask & 0xF000) == 0x3000) {
+ NewEntry.AddrShiftAmount = 24;
+ } else if ((NewEntry.Mask & 0xC000) == 0xC000) {
+ NewEntry.AddrShiftAmount = 26;
+ } else if ((NewEntry.Mask & 0x30000) == 0x30000) {
+ NewEntry.AddrShiftAmount = 28;
+ } else {
+ fatal("Invalid Mask Pattern Detected!\n");
+ }
+ NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
+
+ MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
+ Config3Reg config3 = Config3
+ PageGrainReg pageGrain = PageGrain;
+ int SP = 0;
+ if (bits(config3, config3.sp) == 1 &&
+ bits(pageGrain, pageGrain.esp) == 1) {
+ SP = 1;
+ }
+ IndexReg index = Index;
+ Ptr->insertAt(NewEntry, Index & 0x7FFFFFFF, SP);
}});
0x06: tlbwr({{
- //Create PTE
- MipsISA::PTE NewEntry;
- //Write PTE
- NewEntry.Mask = (Addr)(PageMask >> 11);
- NewEntry.VPN = (Addr)(EntryHi >> 11);
- /* PageGrain _ ESP Config3 _ SP */
- if(((PageGrain>>28) & 1) == 0 || ((Config3>>4)&1) ==0) {
- NewEntry.Mask |= 0x3; // If 1KB pages are *NOT* enabled, lowest bits of the mask are 0b11 for TLB writes
- NewEntry.VPN &= 0xFFFFFFFC; // Reset bits 0 and 1 if 1KB pages are not enabled
- }
- NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
-
- NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
- NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
- NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
- NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
- NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
- NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
- NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
- NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
- NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
- /* Now, compute the AddrShiftAmount and OffsetMask - TLB optimizations */
- /* Addr Shift Amount for 1KB or larger pages */
- // warn("PTE->Mask: %x\n",pte->Mask);
- if((NewEntry.Mask & 0xFFFF) == 3){
- NewEntry.AddrShiftAmount = 12;
- } else if((NewEntry.Mask & 0xFFFF) == 0x0000){
- NewEntry.AddrShiftAmount = 10;
- } else if((NewEntry.Mask & 0xFFFC) == 0x000C){
- NewEntry.AddrShiftAmount = 14;
- } else if((NewEntry.Mask & 0xFFF0) == 0x0030){
- NewEntry.AddrShiftAmount = 16;
- } else if((NewEntry.Mask & 0xFFC0) == 0x00C0){
- NewEntry.AddrShiftAmount = 18;
- } else if((NewEntry.Mask & 0xFF00) == 0x0300){
- NewEntry.AddrShiftAmount = 20;
- } else if((NewEntry.Mask & 0xFC00) == 0x0C00){
- NewEntry.AddrShiftAmount = 22;
- } else if((NewEntry.Mask & 0xF000) == 0x3000){
- NewEntry.AddrShiftAmount = 24;
- } else if((NewEntry.Mask & 0xC000) == 0xC000){
- NewEntry.AddrShiftAmount = 26;
- } else if((NewEntry.Mask & 0x30000) == 0x30000){
- NewEntry.AddrShiftAmount = 28;
- } else {
- fatal("Invalid Mask Pattern Detected!\n");
- }
- NewEntry.OffsetMask = ((1<<NewEntry.AddrShiftAmount)-1);
-
- MipsISA::TLB *Ptr=xc->tcBase()->getITBPtr();
- MiscReg c3=xc->readMiscReg(MipsISA::Config3);
- MiscReg pg=xc->readMiscReg(MipsISA::PageGrain);
- int SP=0;
- if(bits(c3,Config3_SP)==1 && bits(pg,PageGrain_ESP)==1){
- SP=1;
- }
- Ptr->insertAt(NewEntry,Random,SP);
+ //Create PTE
+ MipsISA::PTE NewEntry;
+ //Write PTE
+ NewEntry.Mask = (Addr)(PageMask >> 11);
+ NewEntry.VPN = (Addr)(EntryHi >> 11);
+ /* PageGrain _ ESP Config3 _ SP */
+ if (((PageGrain >> 28) & 1) == 0 ||
+ (( Config3 >> 4) & 1) ==0) {
+ // If 1KB pages are *NOT* enabled, lowest bits of
+ // the mask are 0b11 for TLB writes
+ NewEntry.Mask |= 0x3;
+ // Reset bits 0 and 1 if 1KB pages are not enabled
+ NewEntry.VPN &= 0xFFFFFFFC;
+ }
+ NewEntry.asid = (uint8_t)(EntryHi & 0xFF);
+
+ NewEntry.PFN0 = (Addr)(EntryLo0 >> 6);
+ NewEntry.PFN1 = (Addr)(EntryLo1 >> 6);
+ NewEntry.D0 = (bool)((EntryLo0 >> 2) & 1);
+ NewEntry.D1 = (bool)((EntryLo1 >> 2) & 1);
+ NewEntry.V1 = (bool)((EntryLo1 >> 1) & 1);
+ NewEntry.V0 = (bool)((EntryLo0 >> 1) & 1);
+ NewEntry.G = (bool)((EntryLo0 & EntryLo1) & 1);
+ NewEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7);
+ NewEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7);
+ /* Now, compute the AddrShiftAmount and OffsetMask -
+ TLB optimizations */
+ /* Addr Shift Amount for 1KB or larger pages */
+ if ((NewEntry.Mask & 0xFFFF) == 3){
+ NewEntry.AddrShiftAmount = 12;
+ } else if ((NewEntry.Mask & 0xFFFF) == 0x0000) {
+ NewEntry.AddrShiftAmount = 10;
+ } else if ((NewEntry.Mask & 0xFFFC) == 0x000C) {
+ NewEntry.AddrShiftAmount = 14;
+ } else if ((NewEntry.Mask & 0xFFF0) == 0x0030) {
+ NewEntry.AddrShiftAmount = 16;
+ } else if ((NewEntry.Mask & 0xFFC0) == 0x00C0) {
+ NewEntry.AddrShiftAmount = 18;
+ } else if ((NewEntry.Mask & 0xFF00) == 0x0300) {
+ NewEntry.AddrShiftAmount = 20;
+ } else if ((NewEntry.Mask & 0xFC00) == 0x0C00) {
+ NewEntry.AddrShiftAmount = 22;
+ } else if ((NewEntry.Mask & 0xF000) == 0x3000) {
+ NewEntry.AddrShiftAmount = 24;
+ } else if ((NewEntry.Mask & 0xC000) == 0xC000) {
+ NewEntry.AddrShiftAmount = 26;
+ } else if ((NewEntry.Mask & 0x30000) == 0x30000) {
+ NewEntry.AddrShiftAmount = 28;
+ } else {
+ fatal("Invalid Mask Pattern Detected!\n");
+ }
+ NewEntry.OffsetMask = ((1 << NewEntry.AddrShiftAmount) - 1);
+
+ MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr();
+ Config3Reg config3 = Config3
+ PageGrainReg pageGrain = PageGrain;
+ int SP = 0;
+ if (bits(config3, config3.sp) == 1 &&
+ bits(pageGrain, pageGrain.esp) == 1) {
+ SP = 1;
+ }
+ IndexReg index = Index;
+ Ptr->insertAt(NewEntry, Random, SP);
}});
0x08: tlbp({{
- int TLB_Index;
- Addr VPN;
- if(PageGrain_ESP == 1 && Config3_SP ==1){
- VPN = EntryHi >> 11;
- } else {
- VPN = ((EntryHi >> 11) & 0xFFFFFFFC); // Mask off lower 2 bits
- }
- TLB_Index = xc->tcBase()->getITBPtr()->probeEntry(VPN,EntryHi_ASID);
- if(TLB_Index != -1){ // Check TLB for entry matching EntryHi
- Index=TLB_Index;
- // warn("\ntlbp: Match Found!\n");
- } else {// else, set Index = 1<<31
- Index = (1<<31);
- }
- }});
+ Config3Reg config3 = Config3;
+ PageGrainReg pageGrain = PageGrain;
+ EntryHiReg entryHi = EntryHi;
+ int TLB_Index;
+ Addr VPN;
+ if (pageGrain.esp == 1 && config3.sp ==1) {
+ VPN = EntryHi >> 11;
+ } else {
+ // Mask off lower 2 bits
+ VPN = ((EntryHi >> 11) & 0xFFFFFFFC);
+ }
+ TLB_Index = xc->tcBase()->getITBPtr()->
+ probeEntry(VPN, entryHi.asid);
+ // Check TLB for entry matching EntryHi
+ if (TLB_Index != -1) {
+ Index = TLB_Index;
+ } else {
+ // else, set Index = 1 << 31
+ Index = (1 << 31);
+ }
+ }});
}
format CP0Unimpl {
0x20: wait();
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 1928ee903..4f2d33709 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -85,7 +85,10 @@ output decoder {{
}};
output exec {{
- void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0)
+ void getThrRegExValues(%(CPU_exec_context)s *xc,
+ VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt,
+ TCBindReg &tc_bind, VPEControlReg &vpe_control,
+ MVPConf0Reg &mvp_conf0)
{
vpe_conf0 = xc->readMiscReg(VPEConf0);
tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
@@ -94,7 +97,7 @@ output exec {{
mvp_conf0 = xc->readMiscReg(MVPConf0);
}
- void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
+ void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3)
{
config3 = xc->readMiscReg(Config3);
}
@@ -108,17 +111,19 @@ def template ThreadRegisterExecute {{
%(op_decl)s;
%(op_rd)s;
- unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0;
+ VPEConf0Reg vpeConf0;
+ TCBindReg tcBindMT;
+ TCBindReg tcBind;
+ VPEControlReg vpeControl;
+ MVPConf0Reg mvpConf0;
- getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0);
+ getThrRegExValues(xc, vpeConf0, tcBindMT,
+ tcBind, vpeControl, mvpConf0);
if (isCoprocessorEnabled(xc, 0)) {
- if (bits(vpe_conf0, VPEC0_MVP) == 0 &&
- bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) !=
- bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
+ if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) {
data = -1;
- } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) >
- bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) {
+ } else if (vpeControl.targTC > mvpConf0.ptc) {
data = -1;
} else {
int top_bit = 0;
@@ -154,12 +159,12 @@ def template MTExecute{{
%(op_decl)s;
%(op_rd)s;
- unsigned config3;
+ Config3Reg config3;
getMTExValues(xc, config3);
if (isCoprocessorEnabled(xc, 0)) {
- if (bits(config3, CFG3_MT) == 1) {
+ if (config3.mt == 1) {
%(code)s;
} else {
fault = new ReservedInstructionFault();
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index c2733be9d..1af8857cc 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -140,43 +140,8 @@ def operands {{
'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
-
-
- # named bitfields of Control Regs
- 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
- 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
- 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
- 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
- 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
- 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1),
- 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1),
- 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1),
- 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1),
- 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
- 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4),
- 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4),
- 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1),
- 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
- 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3),
- 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
- 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
- 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1),
- 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
- 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3),
- 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
- 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
- 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1),
-
- # named bitfields of Debug Regs
- 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
- 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
+ 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1),
+ 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1),
#Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index b581d5cf0..0307b37be 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -40,6 +40,7 @@
#include "arch/mips/faults.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/mt_constants.hh"
+#include "arch/mips/pra_constants.hh"
#include "arch/mips/registers.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
@@ -55,16 +56,16 @@ template <class TC>
inline unsigned
getVirtProcNum(TC *tc)
{
- MiscReg tcbind = tc->readMiscRegNoEffect(TCBind);
- return bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
+ TCBindReg tcbind = tc->readMiscRegNoEffect(TCBind);
+ return tcbind.curVPE;
}
template <class TC>
inline unsigned
getTargetThread(TC *tc)
{
- MiscReg vpec_ctrl = tc->readMiscRegNoEffect(VPEControl);
- return bits(vpec_ctrl, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO);
+ VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(VPEControl);
+ return vpeCtrl.targTC;
}
template <class TC>
@@ -107,58 +108,48 @@ template <class TC>
void
forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
{
- int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
+ MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MVPConf0);
+ int num_threads = mvpConf.ptc + 1;
int success = 0;
for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
- unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
- tid);
- unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
+ TCBindReg tidTCBind =
+ tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid);
+ TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind);
- if (bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) ==
- bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
+ if (tidTCBind.curVPE = tcBind.curVPE) {
- unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
- tid);
+ TCStatusReg tidTCStatus =
+ tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag,tid);
- unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
- tid);
+ TCHaltReg tidTCHalt =
+ tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag,tid);
- if (bits(tid_TCStatus, TCS_DA) == 1 &&
- bits(tid_TCHalt, TCH_H) == 0 &&
- bits(tid_TCStatus, TCS_A) == 0 &&
- success == 0) {
-
- tc->setRegOtherThread(MipsISA::TCRestart + Ctrl_Base_DepTag, Rs, tid);
+ if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
+ tidTCStatus.a == 0 && success == 0) {
+ tc->setRegOtherThread(TCRestart + Ctrl_Base_DepTag, Rs, tid);
tc->setRegOtherThread(Rd_bits, Rt, tid);
- unsigned status_ksu = bits(tc->readMiscReg(MipsISA::Status),
- S_KSU_HI, S_KSU_LO);
- unsigned tc_status_asid = bits(tc->readMiscReg(MipsISA::TCStatus),
- TCS_ASID_HI, TCS_ASID_LO);
+ StatusReg status = tc->readMiscReg(Status);
+ TCStatusReg tcStatus = tc->readMiscReg(TCStatus);
// Set Run-State to Running
- replaceBits(tid_TCStatus, TCSTATUS_RNST_HI, TCSTATUS_RNST_LO, 0);
-
+ tidTCStatus.rnst = 0;
// Set Delay-Slot to 0
- replaceBits(tid_TCStatus, TCSTATUS_TDS, 0);
-
+ tidTCStatus.tds = 0;
// Set Dirty TC to 1
- replaceBits(tid_TCStatus, TCSTATUS_DT, 1);
-
+ tidTCStatus.dt = 1;
// Set Activated to 1
- replaceBits(tid_TCStatus, TCSTATUS_A, 1);
-
+ tidTCStatus.a = 1;
// Set status to previous thread's status
- replaceBits(tid_TCStatus, TCSTATUS_TKSU_HI, TCSTATUS_TKSU_LO, status_ksu);
-
+ tidTCStatus.tksu = status.ksu;
// Set ASID to previous thread's state
- replaceBits(tid_TCStatus, TCSTATUS_ASID_HI, TCSTATUS_ASID_LO, tc_status_asid);
+ tidTCStatus.asid = tcStatus.asid;
// Write Status Register
- tc->setRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
- tid_TCStatus, tid);
+ tc->setRegOtherThread(TCStatus + Ctrl_Base_DepTag,
+ tidTCStatus, tid);
// Mark As Successful Fork
success = 1;
@@ -169,8 +160,9 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
}
if (success == 0) {
- unsigned vpe_control = tc->readMiscRegNoEffect(MipsISA::VPEControl);
- tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 1));
+ VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl);
+ vpeControl.excpt = 1;
+ tc->setMiscReg(VPEControl, vpeControl);
fault = new ThreadFault();
}
}
@@ -181,68 +173,54 @@ int
yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
{
if (src_reg == 0) {
- unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
- ThreadID num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
+ MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MVPConf0);
+ ThreadID num_threads = mvpConf0.ptc + 1;
int ok = 0;
// Get Current VPE & TC numbers from calling thread
- unsigned tcbind = tc->readMiscRegNoEffect(TCBind);
- unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
- unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
+ TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind);
for (ThreadID tid = 0; tid < num_threads; tid++) {
- unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
- tid);
- unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,
- tid);
- unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
- tid);
-
- unsigned tid_vpe = bits(tid_TCBind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
- unsigned tid_tc = bits(tid_TCBind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
- unsigned tid_tcstatus_da = bits(tid_TCStatus, TCS_DA);
- unsigned tid_tcstatus_a = bits(tid_TCStatus, TCS_A);
- unsigned tid_tchalt_h = bits(tid_TCHalt, TCH_H);
-
- if (tid_vpe == cur_vpe &&
- tid_tc == cur_tc &&
- tid_tcstatus_da == 1 &&
- tid_tchalt_h == 0 &&
- tid_tcstatus_a == 1) {
+ TCStatusReg tidTCStatus =
+ tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag, tid);
+ TCHaltReg tidTCHalt =
+ tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag, tid);
+ TCBindReg tidTCBind =
+ tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid);
+
+ if (tidTCBind.curVPE == tcBind.curVPE &&
+ tidTCBind.curTC == tcBind.curTC &&
+ tidTCStatus.da == 1 &&
+ tidTCHalt.h == 0 &&
+ tidTCStatus.a == 1) {
ok = 1;
}
}
if (ok == 1) {
- unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
- tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
- warn("%i: Deactivating Hardware Thread Context #%i", curTick, tc->threadId());
+ TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
+ tcStatus.a = 0;
+ tc->setMiscReg(TCStatus, tcStatus);
+ warn("%i: Deactivating Hardware Thread Context #%i",
+ curTick, tc->threadId());
}
} else if (src_reg > 0) {
if (src_reg && !yield_mask != 0) {
- unsigned vpe_control = tc->readMiscReg(VPEControl);
- tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 2));
+ VPEControlReg vpeControl = tc->readMiscReg(VPEControl);
+ vpeControl.excpt = 2;
+ tc->setMiscReg(VPEControl, vpeControl);
fault = new ThreadFault();
} else {
- //tc->setThreadRescheduleCondition(src_reg & yield_mask);
}
} else if (src_reg != -2) {
- unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
- unsigned vpe_control = tc->readMiscRegNoEffect(VPEControl);
- unsigned tcstatus_dt = bits(tcstatus, TCS_DT);
- unsigned vpe_control_ysi = bits(vpe_control, VPEC_YSI);
+ TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
+ VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl);
- if (vpe_control_ysi == 1 && tcstatus_dt == 1 ) {
- tc->setMiscReg(VPEControl, insertBits(vpe_control, VPEC_EXCPT_HI, VPEC_EXCPT_LO, 4));
+ if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) {
+ vpeControl.excpt = 4;
fault = new ThreadFault();
} else {
- //tc->ScheduleOtherThreads();
- //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other Threads.\n" << std::endl;
- //tc->suspend();
- // Save last known PC in TCRestart
- // @TODO: Needs to check if this is a branch and if so, take previous instruction
- //tc->setMiscRegWithEffect(TCRestart, tc->readNextPC());
}
}
@@ -258,17 +236,12 @@ updateStatusView(TC *tc)
{
// TCStatus' register view must be the same as
// Status register view for CU, MX, KSU bits
- MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
- MiscReg status = tc->readMiscRegNoEffect(Status);
-
- unsigned cu_bits = bits(tc_status, TCS_TCU_HI, TCS_TCU_LO);
- replaceBits(status, S_CU_HI, S_CU_LO, cu_bits);
-
- unsigned mx_bits = bits(tc_status, TCS_TMX);
- replaceBits(status, S_MX, S_MX, mx_bits);
+ TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
+ StatusReg status = tc->readMiscRegNoEffect(Status);
- unsigned ksu_bits = bits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO);
- replaceBits(status, S_KSU_HI, S_KSU_LO, ksu_bits);
+ status.cu = tcStatus.tcu;
+ status.mx = tcStatus.tmx;
+ status.ksu = tcStatus.tksu;
tc->setMiscRegNoEffect(Status, status);
}
@@ -281,19 +254,14 @@ updateTCStatusView(TC *tc)
{
// TCStatus' register view must be the same as
// Status register view for CU, MX, KSU bits
- MiscReg tc_status = tc->readMiscRegNoEffect(TCStatus);
- MiscReg status = tc->readMiscRegNoEffect(Status);
-
- unsigned cu_bits = bits(status, S_CU_HI, S_CU_LO);
- replaceBits(tc_status, TCS_TCU_HI, TCS_TCU_LO, cu_bits);
-
- unsigned mx_bits = bits(status, S_MX, S_MX);
- replaceBits(tc_status, TCS_TMX, mx_bits);
+ TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
+ StatusReg status = tc->readMiscRegNoEffect(Status);
- unsigned ksu_bits = bits(status, S_KSU_HI, S_KSU_LO);
- replaceBits(tc_status, TCS_TKSU_HI, TCS_TKSU_LO, ksu_bits);
+ tcStatus.tcu = status.cu;
+ tcStatus.tmx = status.mx;
+ tcStatus.tksu = status.ksu;
- tc->setMiscRegNoEffect(TCStatus, tc_status);
+ tc->setMiscRegNoEffect(TCStatus, tcStatus);
}
} // namespace MipsISA
diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh
index 3f26f5cba..e27798f89 100755
--- a/src/arch/mips/mt_constants.hh
+++ b/src/arch/mips/mt_constants.hh
@@ -33,89 +33,71 @@
#define __ARCH_MIPS_MT_CONSTANTS_HH__
#include "arch/mips/types.hh"
+#include "base/bitunion.hh"
namespace MipsISA
{
-// MVPControl
-const unsigned MVPC_EVP = 0;
-const unsigned MVPC_CUR_VPE_HI = 3;
-const unsigned MVPC_CUR_VPE_LO = 0;
-// MVPConf0
-const unsigned MVPC0_TCA = 15;
-const unsigned MVPC0_PVPE_HI = 13;
-const unsigned MVPC0_PVPE_LO = 10;
-const unsigned MVPC0_PTC_HI = 7;
-const unsigned MVPC0_PTC_LO = 0;
-
-//VPEControl
-const unsigned VPEC_YSI = 21;
-const unsigned VPEC_EXCPT_HI = 18;
-const unsigned VPEC_EXCPT_LO = 16;
-const unsigned VPEC_TE = 15;
-const unsigned VPEC_TARG_TC_HI = 7;
-const unsigned VPEC_TARG_TC_LO = 0;
-
-//VPEConf0
-const unsigned VPEC0_MVP = 1;
-
-//TCBind
-const unsigned TCB_CUR_VPE_HI = 3;
-const unsigned TCB_CUR_VPE_LO = 0;
-const unsigned TCB_CUR_TC_HI = 28;
-const unsigned TCB_CUR_TC_LO = 21;
-
-
-//TCStatus
-const unsigned TCS_TCU_HI = 31;
-const unsigned TCS_TCU_LO = 28;
-const unsigned TCS_TMX = 27;
-const unsigned TCS_DT = 20;
-const unsigned TCS_DA = 15;
-const unsigned TCS_A = 13;
-const unsigned TCS_TKSU_HI = 12;
-const unsigned TCS_TKSU_LO = 11;
-const unsigned TCS_IXMT = 7;
-const unsigned TCS_ASID_HI = 7;
-const unsigned TCS_ASID_LO = 7;
-
-const unsigned TCSTATUS_TCU_HI = 31;
-const unsigned TCSTATUS_TCU_LO = 28;
-const unsigned TCSTATUS_TMX = 27;
-const unsigned TCSTATUS_RNST_HI = 24;
-const unsigned TCSTATUS_RNST_LO = 23;
-const unsigned TCSTATUS_TDS = 21;
-const unsigned TCSTATUS_DT = 20;
-const unsigned TCSTATUS_DA = 15;
-const unsigned TCSTATUS_A = 13;
-const unsigned TCSTATUS_TKSU_HI = 12;
-const unsigned TCSTATUS_TKSU_LO = 11;
-const unsigned TCSTATUS_IXMT = 7;
-const unsigned TCSTATUS_ASID_HI = 7;
-const unsigned TCSTATUS_ASID_LO = 7;
-
-//TCHalt
-const unsigned TCH_H = 0;
-
-//Status
-const unsigned S_CU_HI = 31;
-const unsigned S_CU_LO = 28;
-const unsigned S_MX = 24;
-const unsigned S_KSU_HI = 4;
-const unsigned S_KSU_LO = 3;
-
-// Config0
-const unsigned CFG_M = 31;
-
-// Config1
-const unsigned CFG1_M = 31;
-
-// Config2
-const unsigned CFG2_M = 31;
-
-// Config3
-const unsigned CFG3_M = 31;
-const unsigned CFG3_MT = 2;
+BitUnion32(MVPControlReg)
+ Bitfield<3> cpa;
+ Bitfield<2> stlb;
+ Bitfield<1> vpc;
+ Bitfield<0> evp;
+EndBitUnion(MVPControlReg)
+
+BitUnion32(MVPConf0Reg)
+ Bitfield<31> m;
+ Bitfield<29> tlbs;
+ Bitfield<28> gs;
+ Bitfield<27> pcp;
+ Bitfield<25, 16> ptlbe;
+ Bitfield<15> tca;
+ Bitfield<13, 10> pvpe;
+ Bitfield<7, 0> ptc;
+EndBitUnion(MVPConf0Reg)
+
+BitUnion32(VPEControlReg)
+ Bitfield<21> ysi;
+ Bitfield<18, 16> excpt;
+ Bitfield<15> te;
+ Bitfield<7, 0> targTC;
+EndBitUnion(VPEControlReg)
+
+BitUnion32(VPEConf0Reg)
+ Bitfield<31> m;
+ Bitfield<28, 21> xtc;
+ Bitfield<19> tcs;
+ Bitfield<18> scs;
+ Bitfield<17> dcs;
+ Bitfield<16> ics;
+ Bitfield<1> mvp;
+ Bitfield<0> vpa;
+EndBitUnion(VPEConf0Reg)
+
+BitUnion32(TCBindReg)
+ Bitfield<28, 21> curTC;
+ Bitfield<20, 18> a0;
+ Bitfield<17> tbe;
+ Bitfield<3, 0> curVPE;
+EndBitUnion(TCBindReg)
+
+BitUnion32(TCStatusReg)
+ Bitfield<31, 28> tcu;
+ Bitfield<27> tmx;
+ Bitfield<24, 23> rnst;
+ Bitfield<21> tds;
+ Bitfield<20> dt;
+ Bitfield<19, 16> impl;
+ Bitfield<15> da;
+ Bitfield<13> a;
+ Bitfield<12, 11> tksu;
+ Bitfield<10> ixmt;
+ Bitfield<7, 0> asid;
+EndBitUnion(TCStatusReg)
+
+BitUnion32(TCHaltReg)
+ Bitfield<0> h;
+EndBitUnion(TCHaltReg)
} // namespace MipsISA
diff --git a/src/arch/mips/pra_constants.hh b/src/arch/mips/pra_constants.hh
index 85b33339d..129f4185f 100755
--- a/src/arch/mips/pra_constants.hh
+++ b/src/arch/mips/pra_constants.hh
@@ -32,463 +32,294 @@
#define __ARCH_MIPS_PRA_CONSTANTS_HH__
#include "arch/mips/types.hh"
-//#include "config/full_system.hh"
+#include "base/bitunion.hh"
namespace MipsISA
{
- // See MIPS32(R) Architecture Reference Manual Volume - III
- // This header file uses definitions from Revision 2.50
-
- // Index Status Register - CP0 Reg 0, Sel 0
-
- const unsigned Index_P_HI = 31;
- const unsigned Index_P_LO = 31;
- // Need to figure out how to put in the TLB specific bits here
- // For now, we assume that the entire length is used by the index field
- // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N
- const unsigned Index_HI = 30;
- const unsigned Index_LO = 0;
-
- // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh
-
- // Random Register - CP0 Reg 1, Sel 0
- // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now
- const unsigned Random_HI = 30;
- const unsigned Random_LO = 0;
-
- // EntryLo0 - CP0 Reg2, Sel 0 - Table 8-6, ARM Vol-3
- const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III
- const unsigned EntryLo0_Fill_LO = 30;
- const unsigned EntryLo0_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
- const unsigned EntryLo0_PFN_LO = 6;
- const unsigned EntryLo0_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
- const unsigned EntryLo0_C_LO = 3;
- const unsigned EntryLo0_D_HI = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
- const unsigned EntryLo0_D_LO = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
- const unsigned EntryLo0_V_HI = 1; // Valid Bit
- const unsigned EntryLo0_V_LO = 1; // Valid Bit
- const unsigned EntryLo0_G_HI = 0; // Global Bit. From the ARM Vol-III, Table 8-5:
- const unsigned EntryLo0_G_LO = 0; // Global Bit. From the ARM Vol-III, Table 8-5:
- // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1
- // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are
- // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1
- // reflect the state of the TLB G bit.
-
- // EntryLo1 - CP0 Reg3, Sel 0
- const unsigned EntryLo1_G_HI = 0;
- const unsigned EntryLo1_G_LO = 0;
- const unsigned EntryLo1_V_HI = 1; // Valid Bit
- const unsigned EntryLo1_V_LO = 1; // Valid Bit
- const unsigned EntryLo1_D_HI = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
- const unsigned EntryLo1_D_LO = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception
- const unsigned EntryLo1_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III)
- const unsigned EntryLo1_C_LO = 3;
- const unsigned EntryLo1_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III)
- const unsigned EntryLo1_PFN_LO = 6;
- const unsigned EntryLo1_Fill_LO = 30;
- const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III
-
-
- // Context Register - CP0 Reg 4, Sel 0
- const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array
- const unsigned Context_PTEBase_LO = 23;
- const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the
- const unsigned Context_BadVPN2_LO = 4; // virtual address
- // Bits 3-0 are zeros
-
- // PageMask Register - CP0 Reg 5, Sel 0
- // Bits 31-29 are 0
- const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that
- const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match
- const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III
- const unsigned PageMask_MaskX_LO = 11;
- // Bits 10-0 are zero
-
-
- // PageGrain Register - CP0 Reg 5, Sel 1
- const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS)
- const unsigned PageGrain_ASE_UP_LO = 30; //
- const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32
- const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
- const unsigned PageGrain_ESP_HI = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
- const unsigned PageGrain_ESP_LO = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12
- const unsigned PageGrain_ASE_DN_HI = 12;
- const unsigned PageGrain_ASE_DN_LO = 8;
- // Bits 27-13, 7-0 are zeros
-
- // Wired Register - CPO Reg 6, Sel 0
- // See note on Index register (CP0, Sel0) above
- const unsigned Wired_HI = 30;
- const unsigned Wired_LO = 0;
-
-
- // HWREna Register - CP0 Reg 7, Sel 0
- const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31
- const unsigned HWREna_IMPL_LO = 30; // and 30
- const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible
- const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details
-
-
- // BadVAddr Register - CP0 Reg 8, Sel 0
- const unsigned BadVAddr_HI = 31;
- const unsigned BadVAddr_LO = 0;
-
- // Count Register - CP0 Reg 9, Sel 0
- const unsigned Count_HI = 31;
- const unsigned Count_LO = 0;
-
- // EntryHI Register - CP0 Reg 10, Sel 0
- const unsigned EntryHi_VPN2_HI = 31; // This field is written by hardware on a TLB exception or on a TLB read
- const unsigned EntryHi_VPN2_LO = 13; // and is written by software before a TLB write
- const unsigned EntryHi_VPN2X_HI = 12; // Extension to support 1KB pages
- const unsigned EntryHi_VPN2X_LO = 11;
- const unsigned EntryHi_ASID_HI = 7; // Address space identifier
- const unsigned EntryHi_ASID_LO = 0;
-
- // Compare Register - CP0 Reg 11, Sel 0
- const unsigned Compare_HI = 31; // Used in conjunction with Count
- const unsigned Compare_LO = 0;
-
- // Status Register - CP Reg 12, Sel 0
- const unsigned Status_IE_HI = 0;
- const unsigned Status_IE_LO = 0;
-
- const unsigned Status_EXL = 1;
- const unsigned Status_EXL_HI = 1;
- const unsigned Status_EXL_LO = 1;
- const unsigned Status_ERL_HI = 2;
- const unsigned Status_ERL_LO = 2;
- const unsigned Status_R0 = 3;
- const unsigned Status_UM = 4;
- const unsigned Status_KSU_HI = 4; // R0 and UM are also aliased as KSU
- const unsigned Status_KSU_LO = 3;
- const unsigned Status_UX = 5;
- const unsigned Status_SX = 6;
- const unsigned Status_KX = 7;
- const unsigned Status_IM0 = 8;
- const unsigned Status_IM1 = 9;
- const unsigned Status_IM2 = 10;
- const unsigned Status_IM3 = 11;
- const unsigned Status_IM4 = 12;
- const unsigned Status_IM5 = 13;
- const unsigned Status_IM6 = 14;
- const unsigned Status_IM7 = 15;
- const unsigned Status_IPL_HI = 15; // IM7..IM2 are also aliased as IPL
- const unsigned Status_IPL_LO = 10;
- const unsigned Status_IMPL_HI = 17;
- const unsigned Status_IMPL_LO = 16;
- const unsigned Status_NMI = 19;
- const unsigned Status_SR = 20;
- const unsigned Status_TS = 21;
- const unsigned Status_BEV = 22;
- const unsigned Status_BEV_HI = 22;
- const unsigned Status_BEV_LO = 22;
- const unsigned Status_PX = 23;
- const unsigned Status_MX = 24;
- const unsigned Status_RE = 25;
- const unsigned Status_FR = 26;
- const unsigned Status_RP = 27;
- const unsigned Status_CU3_HI = 31;
- const unsigned Status_CU3_LO = 31;
- const unsigned Status_CU2_HI = 30;
- const unsigned Status_CU2_LO = 30;
- const unsigned Status_CU1_HI = 29;
- const unsigned Status_CU1_LO = 29;
- const unsigned Status_CU0_HI = 28;
- const unsigned Status_CU0_LO = 28;
-
- // IntCtl Register - CP0 Reg 12, Sel 1
- // Interrupt System status and control
- const unsigned IntCtl_IPTI_HI = 31;
- const unsigned IntCtl_IPTI_LO = 29;
- const unsigned IntCtl_IPPCI_HI = 28;
- const unsigned IntCtl_IPPCI_LO = 26;
- const unsigned IntCtl_VS_HI = 9;
- const unsigned IntCtl_VS_LO = 5;
- // Bits 26-10, 4-0 are zeros
-
- // SRSCtl Register - CP0 Reg 12, Sel 2
- // Shadow Register Set Status and Control
- const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set
- const unsigned SRSCtl_HSS_LO=26;
- const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set
- const unsigned SRSCtl_EICSS_LO=18;
- const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set
- const unsigned SRSCtl_ESS_LO=12;
- const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set
- const unsigned SRSCtl_PSS_LO=6;
- const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set
- const unsigned SRSCtl_CSS_LO=0;
-
- // SRSMap Register - CP0 Reg 12, Sel 3
- // Shadow Set IPL mapping
- const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0)
- const unsigned SRSMap_SSV7_LO = 28;
- const unsigned SRSMap_SSV6_HI = 27;
- const unsigned SRSMap_SSV6_LO = 24;
- const unsigned SRSMap_SSV5_HI = 23;
- const unsigned SRSMap_SSV5_LO = 20;
- const unsigned SRSMap_SSV4_HI = 19;
- const unsigned SRSMap_SSV4_LO = 16;
- const unsigned SRSMap_SSV3_HI = 15;
- const unsigned SRSMap_SSV3_LO = 12;
- const unsigned SRSMap_SSV2_HI = 11;
- const unsigned SRSMap_SSV2_LO = 8;
- const unsigned SRSMap_SSV1_HI = 7;
- const unsigned SRSMap_SSV1_LO = 4;
- const unsigned SRSMap_SSV0_HI = 3;
- const unsigned SRSMap_SSV0_LO = 20;
-
- // Cause Register - CP0 Reg 13, Sel 0
- const unsigned Cause_BD_HI = 31;
- const unsigned Cause_BD_LO = 31;
- const unsigned Cause_TI_HI = 30;
- const unsigned Cause_TI_LO = 30;
- const unsigned Cause_CE_HI = 29;
- const unsigned Cause_CE_LO = 28;
- const unsigned Cause_DC = 27;
- const unsigned Cause_PCI = 26;
- const unsigned Cause_IV = 24;
- const unsigned Cause_WP = 23;
- const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5
- const unsigned Cause_RIPL_LO = 10;
- const unsigned Cause_IP7 = 15;
- const unsigned Cause_IP6 = 14;
- const unsigned Cause_IP5 = 13;
- const unsigned Cause_IP4 = 12;
- const unsigned Cause_IP3 = 11;
- const unsigned Cause_IP2 = 10;
- const unsigned Cause_IP1 = 9;
- const unsigned Cause_IP0 = 8;
- const unsigned Cause_EXCCODE_HI = 6;
- const unsigned Cause_EXCCODE_LO = 2;
- // All intermediate undefined bits must be ZERO
-
-
- // EPC Register - CP0 Reg 14, Sel 0
- // Exception Program Counter
- const unsigned EPC_HI = 31;
- const unsigned EPC_LO = 0;
-
- // PRId Register - CP0 Reg 15, Sel 0
- // Processor Identification register
- const unsigned PRIdCoOp_HI = 31;
- const unsigned PRIdCoOp_LO = 24;
- const unsigned PRIdCoID_HI = 23;
- const unsigned PRIdCoID_LO = 16;
- const unsigned PRIdProc_ID_HI = 15;
- const unsigned PRIdProc_ID_LO = 8;
- const unsigned PRIdRev_HI = 7;
- const unsigned PRIdRev_LO = 0;
-
-
- // EBase Register - CP0 Reg 15, Sel 1
- // Exception Base Register
- const unsigned EBase_MSB = 31; // MUST BE = 1
- const unsigned EBase_EXCEPTION_Base_HI = 29;
- const unsigned EBase_EXCEPTION_Base_LO = 12;
- const unsigned EBase_CPUNum_HI = 9;
- const unsigned EBase_CPUNum_LO = 0;
- // Undefined bits must be zero
-
- // Config Register - CP0 Reg 16, Sel 0
- const unsigned Config_M = 31;
- const unsigned Config_K23_HI = 30;
- const unsigned Config_K23_LO = 28;
- const unsigned Config_KU_HI = 27;
- const unsigned Config_KU_LO = 25;
- const unsigned Config_IMPL_HI = 24;
- const unsigned Config_IMPL_LO = 16;
- const unsigned Config_BE_HI = 15;
- const unsigned Config_BE_LO = 15;
- const unsigned Config_AT_HI = 14;
- const unsigned Config_AT_LO = 13;
- const unsigned Config_AR_HI = 12;
- const unsigned Config_AR_LO = 10;
- const unsigned Config_MT_HI = 9;
- const unsigned Config_MT_LO = 7;
- const unsigned Config_VI_HI = 3;
- const unsigned Config_VI_LO = 3;
- const unsigned Config_K0_HI = 2;
- const unsigned Config_K0_LO = 0;
-
- // Config1 Register - CP0 Reg 16, Sel 1
- const unsigned Config1_M = 31;
- const unsigned Config1_MMUSize_HI = 30;
- const unsigned Config1_MMUSize_LO = 25;
- const unsigned Config1_IS_HI = 24;
- const unsigned Config1_IS_LO = 22;
- const unsigned Config1_IL_HI = 21;
- const unsigned Config1_IL_LO = 19;
- const unsigned Config1_IA_HI = 18;
- const unsigned Config1_IA_LO = 16;
- const unsigned Config1_DS_HI = 15;
- const unsigned Config1_DS_LO = 13;
- const unsigned Config1_DL_HI = 12;
- const unsigned Config1_DL_LO = 10;
- const unsigned Config1_DA_HI = 9;
- const unsigned Config1_DA_LO = 7;
- const unsigned Config1_C2_HI = 6;
- const unsigned Config1_C2_LO = 6;
- const unsigned Config1_MD_HI = 5;
- const unsigned Config1_MD_LO = 5;
- const unsigned Config1_PC_HI = 4;
- const unsigned Config1_PC_LO = 4;
- const unsigned Config1_WR_HI = 3;
- const unsigned Config1_WR_LO = 3;
- const unsigned Config1_CA_HI = 2;
- const unsigned Config1_CA_LO = 2;
- const unsigned Config1_EP_HI = 1;
- const unsigned Config1_EP_LO = 1;
- const unsigned Config1_FP_HI = 0;
- const unsigned Config1_FP_LO = 0;
-
-
- // Config2 Register - CP0 Reg 16, Sel 2
- const unsigned Config2_M = 31;
- const unsigned Config2_TU_HI = 30;
- const unsigned Config2_TU_LO = 28;
- const unsigned Config2_TS_HI = 27;
- const unsigned Config2_TS_LO = 24;
- const unsigned Config2_TL_HI = 23;
- const unsigned Config2_TL_LO = 20;
- const unsigned Config2_TA_HI = 19;
- const unsigned Config2_TA_LO = 16;
- const unsigned Config2_SU_HI = 15;
- const unsigned Config2_SU_LO = 12;
- const unsigned Config2_SS_HI = 11;
- const unsigned Config2_SS_LO = 8;
- const unsigned Config2_SL_HI = 7;
- const unsigned Config2_SL_LO = 4;
- const unsigned Config2_SA_HI = 3;
- const unsigned Config2_SA_LO = 0;
-
- // Config3 Register - CP0 Reg 16, Sel 3
- const unsigned Config3_M = 31;
- const unsigned Config3_DSPP_HI = 10;
- const unsigned Config3_DSPP_LO = 10;
- const unsigned Config3_LPA_HI=7;
- const unsigned Config3_LPA_LO=7;
- const unsigned Config3_VEIC_HI=6;
- const unsigned Config3_VEIC_LO=6;
- const unsigned Config3_VINT_HI=5;
- const unsigned Config3_VINT_LO=5;
- const unsigned Config3_SP=4;
- const unsigned Config3_SP_HI=4;
- const unsigned Config3_SP_LO=4;
- const unsigned Config3_MT_HI=2;
- const unsigned Config3_MT_LO=2;
- const unsigned Config3_SM_HI=1;
- const unsigned Config3_SM_LO=1;
- const unsigned Config3_TL_HI=0;
- const unsigned Config3_TL_LO=0;
-
-
- // LLAddr Register - CP0 Reg 17, Sel 0
- // Load Linked Address (Physical)
- const unsigned LLAddr_PAddr_HI = 31;
- const unsigned LLAddr_PAddr_LO = 0;
-
-
-
- // WatchLo Register - CP0 Reg 18, Sel 0-n
- // See WatchHi to determine how many pairs of these registers are available
- const unsigned WatchLo_VAddr_HI = 31;
- const unsigned WatchLo_VAddr_LO = 3;
- const unsigned WatchLo_I = 2;
- const unsigned WatchLo_R = 1;
- const unsigned WatchLo_W = 0;
-
-
- // WatchHi Register - CP0 Reg 19, Sel 0-n
- const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist
- const unsigned WatchHi_G = 30;
- const unsigned WatchHi_ASID_HI = 23;
- const unsigned WatchHi_ASID_LO = 16;
- const unsigned WatchHi_Mask_HI = 11;
- const unsigned WatchHi_Mask_LO = 3;
- const unsigned WatchHi_I = 2;
- const unsigned WatchHi_R = 1;
- const unsigned WatchHi_W = 0;
-
- // Debug Register - CP0 Reg 23, Sel 0
-
- // TraceControl Register - CP0 Reg 23, Sel 1
- // TraceControl2 Register - CP0 Reg 23, Sel 2
- // UserTraceData Register - CP0 Reg 23, Sel 3
- // TraceBPC Register - CP0 Reg 23, Sel 4
- // DEPC Register - CP0 Reg 24, Sel 0
-
-
- // PerfCnt Register - CP0 Reg 25, Sel 0-n
- // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25
- // Even values are control registers, odd values are the actual counter
- // The format for the control reg is:
- const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers?
- const unsigned PerfCntCtl_W = 30;
- const unsigned PerfCntCtl_Event_HI = 10;
- const unsigned PerfCntCtl_Event_LO = 5;
- const unsigned PerfCntCtl_IE = 4;
- const unsigned PerfCntCtl_U = 3;
- const unsigned PerfCntCtl_S = 2;
- const unsigned PerfCntCtl_K = 1;
- const unsigned PerfCntCtl_EXL = 0;
-
- // The format for the counter is a 32-bit value (or 64-bit for MIPS64)
- const unsigned PerfCnt_Count_HI = 31;
- const unsigned PerfCnt_Count_LO = 0;
-
- // ErrCtl Register - CP0 Reg 26, Sel 0
- // This is implementation dependent, not defined by the ISA
-
- // CacheErr Register - CP0 Reg 27, Sel 0
- // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3)
- // used by the CacheErr registers. However, on page 134, only one sel value is shown
- const unsigned Cache_Err_ER = 31;
- const unsigned Cache_Err_EC = 30;
- const unsigned Cache_Err_ED = 29;
- const unsigned Cache_Err_ET = 28;
- const unsigned Cache_Err_ES = 27;
- const unsigned Cache_Err_EE = 26;
- const unsigned Cache_Err_EB = 25;
- const unsigned Cache_Err_IMPL_HI = 24;
- const unsigned Cache_Err_IMPL_LO = 22;
- const unsigned Cache_Err_Index_HI = 21;
- const unsigned Cache_Err_Index_LO = 0;
-
- // TagLo Register - CP0 Reg 28 - Even Selects (0,2)
- const unsigned TagLo_PTagLo_HI = 31;
- const unsigned TagLo_PTagLo_LO = 8;
- const unsigned TagLo_PState_HI = 7;
- const unsigned TagLo_PState_LO = 6;
- const unsigned TagLo_L = 5;
- const unsigned TagLo_IMPL_HI = 4;
- const unsigned TagLo_IMPL_LO = 3;
- const unsigned TagLo_P = 0;
- // undefined bits must be written 0
-
-
- // DataLo Register - CP0 Reg 28 - Odd Selects (1,3)
- const unsigned DataLo_HI = 31;
- const unsigned DataLo_LO = 0;
-
- // TagHi Register - CP0 Reg 29 - Even Selects (0,2)
- // Not defined by the architecture
-
- // DataHi Register - CP0 Reg 29 - Odd Selects (1,3)
- const unsigned DataHi_HI = 31;
- const unsigned DataHi_LO = 0;
-
-
- // ErrorEPC - CP0 Reg 30, Sel 0
- const unsigned ErrorPC_HI = 31;
- const unsigned ErrorPC_LO = 0;
-
- // DESAVE - CP0 Reg 31, Sel 0
-
-
-
+BitUnion32(IndexReg)
+ Bitfield<31> p;
+ // Need to figure out how to put in the TLB specific bits here
+ // For now, we assume that the entire length is used by the index
+ // field In reality, Index_HI = N-1, where
+ // N = Ceiling(log2(TLB Entries))
+ Bitfield<30, 0> index;
+EndBitUnion(IndexReg)
+
+BitUnion32(RandomReg)
+ // This has a problem similar to the IndexReg index field. We'll keep
+ // both consistent at 30 for now
+ Bitfield<30, 0> random;
+EndBitUnion(RandomReg)
+
+BitUnion64(EntryLoReg)
+ Bitfield<63, 30> fill;
+ Bitfield<29, 6> pfn; // Page frame number
+ Bitfield<5, 3> c; // Coherency attribute
+ Bitfield<2> d; // Dirty Bit
+ Bitfield<1> v; // Valid Bit
+ Bitfield<0> g; // Global Bit
+EndBitUnion(EntryLoReg)
+
+BitUnion64(ContextReg)
+ Bitfield<63, 23> pteBase;
+ Bitfield<22, 4> badVPN2;
+ // Bits 3-0 are 0
+EndBitUnion(ContextReg)
+
+BitUnion32(PageMaskReg)
+ // Bits 31-29 are 0
+ Bitfield<28, 13> mask;
+ Bitfield<12, 11> maskx;
+ // Bits 10-0 are zero
+EndBitUnion(PageMaskReg)
+
+BitUnion32(PageGrainReg)
+ Bitfield<31, 30> aseUp;
+ Bitfield<29> elpa;
+ Bitfield<28> esp;
+ // Bits 27-13 are zeros
+ Bitfield<12, 8> aseDn;
+ // Bits 7-0 are zeros
+EndBitUnion(PageGrainReg)
+
+BitUnion32(WiredReg)
+ // See note on Index register above
+ Bitfield<30, 0> wired;
+EndBitUnion(WiredReg)
+
+BitUnion32(HWREnaReg)
+ Bitfield<31, 30> impl;
+ Bitfield<3, 0> mask;
+EndBitUnion(HWREnaReg)
+
+BitUnion64(EntryHiReg)
+ Bitfield<63, 62> r;
+ Bitfield<61, 40> fill;
+ Bitfield<39, 13> vpn2;
+ Bitfield<12, 11> vpn2x;
+ Bitfield<7, 0> asid;
+EndBitUnion(EntryHiReg)
+
+BitUnion32(StatusReg)
+ SubBitUnion(cu, 31, 28)
+ Bitfield<31> cu3;
+ Bitfield<30> cu2;
+ Bitfield<29> cu1;
+ Bitfield<28> cu0;
+ EndSubBitUnion(cu)
+ Bitfield<27> rp;
+ Bitfield<26> fr;
+ Bitfield<25> re;
+ Bitfield<24> mx;
+ Bitfield<23> px;
+ Bitfield<22> bev;
+ Bitfield<21> ts;
+ Bitfield<20> sr;
+ Bitfield<19> nmi;
+ // Bit 18 is zero
+ Bitfield<17, 16> impl;
+ Bitfield<15, 10> ipl;
+ Bitfield<15> im7;
+ Bitfield<14> im6;
+ Bitfield<13> im5;
+ Bitfield<12> im4;
+ Bitfield<11> im3;
+ Bitfield<10> im2;
+ Bitfield<9> im1;
+ Bitfield<8> im0;
+ Bitfield<7> kx;
+ Bitfield<6> sx;
+ Bitfield<5> ux;
+ Bitfield<4, 3> ksu;
+ Bitfield<4> um;
+ Bitfield<3> r0;
+ Bitfield<2> erl;
+ Bitfield<1> exl;
+ Bitfield<0> ie;
+EndBitUnion(StatusReg)
+
+BitUnion32(IntCtlReg)
+ Bitfield<31, 29> ipti;
+ Bitfield<28, 26> ippci;
+ // Bits 26-10 are zeros
+ Bitfield<9, 5> vs;
+ // Bits 4-0 are zeros
+EndBitUnion(IntCtlReg)
+
+BitUnion32(SRSCtlReg)
+ // Bits 31-30 are zeros
+ Bitfield<29, 26> hss;
+ // Bits 25-22 are zeros
+ Bitfield<21, 18> eicss;
+ // Bits 17-16 are zeros
+ Bitfield<15, 12> ess;
+ // Bits 11-10 are zeros
+ Bitfield<9, 6> pss;
+ // Bits 5-4 are zeros
+ Bitfield<3, 0> css;
+EndBitUnion(SRSCtlReg)
+
+BitUnion32(SRSMapReg)
+ Bitfield<31, 28> ssv7;
+ Bitfield<27, 24> ssv6;
+ Bitfield<23, 20> ssv5;
+ Bitfield<19, 16> ssv4;
+ Bitfield<15, 12> ssv3;
+ Bitfield<11, 8> ssv2;
+ Bitfield<7, 4> ssv1;
+ Bitfield<3, 0> ssv0;
+EndBitUnion(SRSMapReg)
+
+BitUnion32(CauseReg)
+ Bitfield<31> bd;
+ Bitfield<30> ti;
+ Bitfield<29, 28> ce;
+ Bitfield<27> dc;
+ Bitfield<26> pci;
+ // Bits 25-24 are zeros
+ Bitfield<23> iv;
+ Bitfield<22> wp;
+ // Bits 21-16 are zeros
+ Bitfield<15, 10> ripl;
+ Bitfield<15> ip7;
+ Bitfield<14> ip6;
+ Bitfield<13> ip5;
+ Bitfield<12> ip4;
+ Bitfield<11> ip3;
+ Bitfield<10> ip2;
+ Bitfield<9> ip1;
+ Bitfield<8> ip0;
+ // Bit 7 is zero
+ Bitfield<6, 2> excCode;
+ // Bits 1-0 are zeros
+EndBitUnion(CauseReg)
+
+BitUnion32(PRIdReg)
+ Bitfield<31, 24> coOp;
+ Bitfield<23, 16> coId;
+ Bitfield<15, 8> procId;
+ Bitfield<7, 0> rev;
+EndBitUnion(PRIdReg)
+
+BitUnion32(EBaseReg)
+ // Bit 31 is one
+ // Bit 30 is zero
+ Bitfield<29, 12> exceptionBase;
+ // Bits 11-10 are zeros
+ Bitfield<9, 9> cpuNum;
+EndBitUnion(EBaseReg)
+
+BitUnion32(ConfigReg)
+ Bitfield<31> m;
+ Bitfield<30, 28> k23;
+ Bitfield<27, 25> ku;
+ Bitfield<24, 16> impl;
+ Bitfield<15> be;
+ Bitfield<14, 13> at;
+ Bitfield<12, 10> ar;
+ Bitfield<9, 7> mt;
+ // Bits 6-4 are zeros
+ Bitfield<3> vi;
+ Bitfield<2, 0> k0;
+EndBitUnion(ConfigReg)
+
+BitUnion32(Config1Reg)
+ Bitfield<31> m;
+ Bitfield<30, 25> mmuSize;
+ Bitfield<24, 22> is;
+ Bitfield<21, 19> il;
+ Bitfield<18, 16> ia;
+ Bitfield<15, 13> ds;
+ Bitfield<12, 10> dl;
+ Bitfield<9, 7> da;
+ Bitfield<6> c2;
+ Bitfield<5> md;
+ Bitfield<4> pc;
+ Bitfield<3> wr;
+ Bitfield<2> ca;
+ Bitfield<1> ep;
+ Bitfield<0> fp;
+EndBitUnion(Config1Reg)
+
+BitUnion32(Config2Reg)
+ Bitfield<31> m;
+ Bitfield<30, 28> tu;
+ Bitfield<27, 24> ts;
+ Bitfield<23, 20> tl;
+ Bitfield<19, 16> ta;
+ Bitfield<15, 12> su;
+ Bitfield<11, 8> ss;
+ Bitfield<7, 4> sl;
+ Bitfield<3, 0> sa;
+EndBitUnion(Config2Reg)
+
+BitUnion32(Config3Reg)
+ Bitfield<31> m;
+ // Bits 30-11 are zeros
+ Bitfield<10> dspp;
+ // Bits 9-8 are zeros
+ Bitfield<7> lpa;
+ Bitfield<6> veic;
+ Bitfield<5> vint;
+ Bitfield<4> sp;
+ // Bit 3 is zero
+ Bitfield<2> mt;
+ Bitfield<1> sm;
+ Bitfield<0> tl;
+EndBitUnion(Config3Reg)
+
+BitUnion64(WatchLoReg)
+ Bitfield<63, 3> vaddr;
+ Bitfield<2> i;
+ Bitfield<1> r;
+ Bitfield<0> w;
+EndBitUnion(WatchLoReg)
+
+BitUnion32(WatchHiReg)
+ Bitfield<31> m;
+ Bitfield<30> g;
+ // Bits 29-24 are zeros
+ Bitfield<23, 16> asid;
+ // Bits 15-12 are zeros
+ Bitfield<11, 3> mask;
+ Bitfield<2> i;
+ Bitfield<1> r;
+ Bitfield<0> w;
+EndBitUnion(WatchHiReg)
+
+BitUnion32(PerfCntCtlReg)
+ Bitfield<31> m;
+ Bitfield<30> w;
+ // Bits 29-11 are zeros
+ Bitfield<10, 5> event;
+ Bitfield<4> ie;
+ Bitfield<3> u;
+ Bitfield<2> s;
+ Bitfield<1> k;
+ Bitfield<0> exl;
+EndBitUnion(PerfCntCtlReg)
+
+BitUnion32(CacheErrReg)
+ Bitfield<31> er;
+ Bitfield<30> ec;
+ Bitfield<29> ed;
+ Bitfield<28> et;
+ Bitfield<27> es;
+ Bitfield<26> ee;
+ Bitfield<25> eb;
+ Bitfield<24, 22> impl;
+ Bitfield<22, 0> index;
+EndBitUnion(CacheErrReg)
+
+BitUnion32(TagLoReg)
+ Bitfield<31, 8> pTagLo;
+ Bitfield<7, 6> pState;
+ Bitfield<5> l;
+ Bitfield<4, 3> impl;
+ // Bits 2-1 are zeros
+ Bitfield<0> p;
+EndBitUnion(TagLoReg)
} // namespace MipsISA
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