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| author | Andrew Lukefahr <lukefahr@umich.edu> | 2015-01-03 17:51:48 -0600 |
|---|---|---|
| committer | Andrew Lukefahr <lukefahr@umich.edu> | 2015-01-03 17:51:48 -0600 |
| commit | 6d3200440702719356ee337fc7f24075cdb75224 (patch) | |
| tree | 7c2f3daf5a04d57292dc5fb0295538f0aa6fdc14 /src | |
| parent | cb911559dc04226edef89ff37636dbb17aad5604 (diff) | |
| download | gem5-6d3200440702719356ee337fc7f24075cdb75224.tar.xz | |
minor: fixed LSQ MasterPortID
Minor was reporting the data cache access as ".inst" accesses.
This just switches the MasterPortID to dataMasterPortId.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/minor/lsq.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc index 501620746..49daa3518 100644 --- a/src/cpu/minor/lsq.cc +++ b/src/cpu/minor/lsq.cc @@ -1503,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0); request->request.setVirt(0 /* asid */, - addr, size, flags, cpu.instMasterId(), + addr, size, flags, cpu.dataMasterId(), /* I've no idea why we need the PC, but give it */ inst->pc.instAddr()); |