arch: Add support for invalidating TLBs when draining

This patch adds support for the memInvalidate() drain method.  TLB
flushing is requested by calling the virtual flushAll() method on the
TLB.

Note: This patch renames invalidateAll() to flushAll() on x86 and
SPARC to make the interface consistent across all supported
architectures.

7 files changed, 21 insertions, 16 deletions

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 9faf297d6..5d6dfe2c3 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -323,7 +323,7 @@ TLB::demapAll(int partition_id)
 }
 
 void
-TLB::invalidateAll()
+TLB::flushAll()
 {
     cacheValid = false;
     lookupTable.clear();
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index abbe2df3c..8ed10ff0e 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -123,7 +123,7 @@ class TLB : public BaseTLB
     uint64_t TagRead(int entry);
 
     /** Remove all entries from the TLB */
-    void invalidateAll();
+    void flushAll();
 
     /** Remove all non-locked entries from the tlb that match partition id. */
     void demapAll(int partition_id);
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 9dbab8c7e..852ce6bc8 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -191,8 +191,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
                 }
             }
             if (toggled.pg) {
-                tc->getITBPtr()->invalidateAll();
-                tc->getDTBPtr()->invalidateAll();
+                tc->getITBPtr()->flushAll();
+                tc->getDTBPtr()->flushAll();
             }
             //This must always be 1.
             newCR0.et = 1;
@@ -208,15 +208,15 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
       case MISCREG_CR2:
         break;
       case MISCREG_CR3:
-        tc->getITBPtr()->invalidateNonGlobal();
-        tc->getDTBPtr()->invalidateNonGlobal();
+        tc->getITBPtr()->flushNonGlobal();
+        tc->getDTBPtr()->flushNonGlobal();
         break;
       case MISCREG_CR4:
         {
             CR4 toggled = regVal[miscReg] ^ val;
             if (toggled.pae || toggled.pse || toggled.pge) {
-                tc->getITBPtr()->invalidateAll();
-                tc->getDTBPtr()->invalidateAll();
+                tc->getITBPtr()->flushAll();
+                tc->getDTBPtr()->flushAll();
             }
         }
         break;
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index fb7dac02e..33de0129a 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -129,7 +129,7 @@ TLB::lookup(Addr va, bool update_lru)
 }
 
 void
-TLB::invalidateAll()
+TLB::flushAll()
 {
     DPRINTF(TLB, "Invalidating all entries.\n");
     for (unsigned i = 0; i < size; i++) {
@@ -148,7 +148,7 @@ TLB::setConfigAddress(uint32_t addr)
 }
 
 void
-TLB::invalidateNonGlobal()
+TLB::flushNonGlobal()
 {
     DPRINTF(TLB, "Invalidating all non global entries.\n");
     for (unsigned i = 0; i < size; i++) {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 85bcead57..39ae240af 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -75,8 +75,6 @@ namespace X86ISA
         typedef X86TLBParams Params;
         TLB(const Params *p);
 
-        void dumpAll();
-
         TlbEntry *lookup(Addr va, bool update_lru = true);
 
         void setConfigAddress(uint32_t addr);
@@ -90,9 +88,9 @@ namespace X86ISA
       public:
         Walker *getWalker();
 
-        void invalidateAll();
+        void flushAll();
 
-        void invalidateNonGlobal();
+        void flushNonGlobal();
 
         void demapPage(Addr va, uint64_t asn);
 
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 65c1a9d32..e56e96b99 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -213,8 +213,8 @@ copyMiscRegs(ThreadContext *src, ThreadContext *dest)
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
     }
 
-    dest->getITBPtr()->invalidateAll();
-    dest->getDTBPtr()->invalidateAll();
+    dest->getITBPtr()->flushAll();
+    dest->getDTBPtr()->flushAll();
 }
 
 void
diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index aadf047bf..95a252e16 100644
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -65,6 +65,11 @@ class BaseTLB : public SimObject
     virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
 
     /**
+     * Remove all entries from the TLB
+     */
+    virtual void flushAll() = 0;
+
+    /**
      * Get the table walker master port if present. This is used for
      * migrating port connections during a CPU takeOverFrom()
      * call. For architectures that do not have a table walker, NULL
@@ -75,6 +80,8 @@ class BaseTLB : public SimObject
      */
     virtual BaseMasterPort* getMasterPort() { return NULL; }
 
+    void memInvalidate() { flushAll(); }
+
     class Translation
     {
       public: