SE/FS: Turn on the page table class in FS.

7 files changed, 64 insertions, 74 deletions

diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index cd269f1af..8678eb7e4 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -34,34 +34,14 @@
 #ifndef __ARCH_MIPS_PAGETABLE_H__
 #define __ARCH_MIPS_PAGETABLE_H__
 
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
 
 namespace MipsISA {
 
 struct VAddr
 {
-    static const int ImplBits = 43;
-    static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
-    static const Addr UnImplMask = ~ImplMask;
-
-    VAddr(Addr a) : addr(a) {}
-    Addr addr;
-    operator Addr() const { return addr; }
-    const VAddr &operator=(Addr a) { addr = a; return *this; }
-
-    Addr vpn() const { return (addr & ImplMask) >> PageShift; }
-    Addr page() const { return addr & Page_Mask; }
-    Addr offset() const { return addr & PageOffset; }
-
-    Addr level3() const
-    { return MipsISA::PteAddr(addr >> PageShift); }
-    Addr level2() const
-    { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
-    Addr level1() const
-    { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
 };
 
 // ITB/DTB page table entry
@@ -98,6 +78,33 @@ struct PTE
     void unserialize(Checkpoint *cp, const std::string &section);
 };
 
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+struct TlbEntry
+{
+    Addr _pageStart;
+    TlbEntry() {}
+    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
+    Addr pageStart()
+    {
+        return _pageStart;
+    }
+
+    void
+    updateVaddr(Addr new_vaddr) {}
+
+    void serialize(std::ostream &os)
+    {
+        SERIALIZE_SCALAR(_pageStart);
+    }
+
+    void unserialize(Checkpoint *cp, const std::string &section)
+    {
+        UNSERIALIZE_SCALAR(_pageStart);
+    }
+
+};
+
 };
 #endif // __ARCH_MIPS_PAGETABLE_H__
 
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 4b1456862..834431536 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -55,33 +55,6 @@ class ThreadContext;
    simply create an ITLB and DTLB that will point to the real TLB */
 namespace MipsISA {
 
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
-    Addr _pageStart;
-    TlbEntry() {}
-    TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
-    Addr pageStart()
-    {
-        return _pageStart;
-    }
-
-    void
-    updateVaddr(Addr new_vaddr) {}
-    
-    void serialize(std::ostream &os)
-    {
-        SERIALIZE_SCALAR(_pageStart);
-    }
-
-    void unserialize(Checkpoint *cp, const std::string &section)
-    {
-        UNSERIALIZE_SCALAR(_pageStart);
-    }
-
-};
-
 class TLB : public BaseTLB
 {
   protected:
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 8995ed736..da37edb57 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -46,12 +46,10 @@ Source('vport.cc')
 if env['TARGET_ISA'] != 'no':
     SimObject('PhysicalMemory.py')
     Source('dram.cc')
+    Source('page_table.cc')
     Source('physical.cc')
     Source('translating_port.cc')
 
-if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
-    Source('page_table.cc')
-
 DebugFlag('Bus')
 DebugFlag('BusAddrRanges')
 DebugFlag('BusBridge')
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index a94d92480..a2d566d0c 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -52,9 +52,15 @@
 using namespace std;
 using namespace TheISA;
 
-PageTable::PageTable(Process *_process, Addr _pageSize)
-    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
-      process(_process)
+PageTable::PageTable(
+#if !FULL_SYSTEM
+        Process *_process,
+#endif
+        Addr _pageSize)
+    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize)))
+#if !FULL_SYSTEM
+      , process(_process)
+#endif
 {
     assert(isPowerOf2(pageSize));
     pTableCache[0].vaddr = 0;
@@ -83,9 +89,11 @@ PageTable::allocate(Addr vaddr, int64_t size)
                     vaddr);
         }
 
+#if !FULL_SYSTEM
         pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
                 process->system->new_page());
         updateCache(vaddr, pTable[vaddr]);
+#endif
     }
 }
 
@@ -196,7 +204,9 @@ PageTable::serialize(std::ostream &os)
     PTableItr iter = pTable.begin();
     PTableItr end = pTable.end();
     while (iter != end) {
+#if !FULL_SYSTEM
         os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
+#endif
 
         paramOut(os, "vaddr", iter->first);
         iter->second.serialize(os);
@@ -212,17 +222,20 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
 {
     int i = 0, count;
     paramIn(cp, section, "ptable.size", count);
-    Addr vaddr;
-    TheISA::TlbEntry *entry;
 
     pTable.clear();
 
-    while(i < count) {
+    while (i < count) {
+#if !FULL_SYSTEM
+        TheISA::TlbEntry *entry;
+        Addr vaddr;
+
         paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr);
         entry = new TheISA::TlbEntry();
         entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
         pTable[vaddr] = *entry;
         ++i;
+#endif
     }
 }
 
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 61da5f322..37bc808e7 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -42,11 +42,14 @@
 #include "arch/tlb.hh"
 #include "base/hashmap.hh"
 #include "base/types.hh"
+#include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "mem/request.hh"
 #include "sim/serialize.hh"
 
+#if !FULL_SYSTEM
 class Process;
+#endif
 
 /**
  * Page Table Declaration.
@@ -68,11 +71,17 @@ class PageTable
     const Addr pageSize;
     const Addr offsetMask;
 
+#if !FULL_SYSTEM
     Process *process;
+#endif
 
   public:
 
-    PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
+    PageTable(
+#if !FULL_SYSTEM
+            Process *_process,
+#endif
+            Addr _pageSize = TheISA::VMPageSize);
 
     ~PageTable();
 
diff --git a/src/mem/translating_port.cc b/src/mem/translating_port.cc
index ebfed1281..260871874 100644
--- a/src/mem/translating_port.cc
+++ b/src/mem/translating_port.cc
@@ -35,9 +35,7 @@
 #include "base/chunk_generator.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
-#if !FULL_SYSTEM
 #include "mem/page_table.hh"
-#endif
 #include "mem/port.hh"
 #include "mem/translating_port.hh"
 #if !FULL_SYSTEM
@@ -67,14 +65,12 @@ TranslatingPort::tryReadBlob(Addr addr, uint8_t *p, int size)
     int prevSize = 0;
 
     for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-#if !FULL_SYSTEM
         Addr paddr;
 
         if (!pTable->translate(gen.addr(),paddr))
             return false;
 
         Port::readBlob(paddr, p + prevSize, gen.size());
-#endif
         prevSize += gen.size();
     }
 
@@ -95,7 +91,6 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
     int prevSize = 0;
 
     for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-#if !FULL_SYSTEM
         Addr paddr;
 
         if (!pTable->translate(gen.addr(), paddr)) {
@@ -104,9 +99,11 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
                                  VMPageSize);
             } else if (allocating == NextPage) {
                 // check if we've accessed the next page on the stack
+#if !FULL_SYSTEM
                 if (!process->fixupStackFault(gen.addr()))
                     panic("Page table fault when accessing virtual address %#x "
                             "during functional write\n", gen.addr());
+#endif
             } else {
                 return false;
             }
@@ -114,7 +111,6 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size)
         }
 
         Port::writeBlob(paddr, p + prevSize, gen.size());
-#endif
         prevSize += gen.size();
     }
 
@@ -133,7 +129,6 @@ bool
 TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
 {
     for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-#if !FULL_SYSTEM
         Addr paddr;
 
         if (!pTable->translate(gen.addr(), paddr)) {
@@ -146,7 +141,6 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
             }
         }
         Port::memsetBlob(paddr, val, gen.size());
-#endif
     }
 
     return true;
@@ -163,7 +157,6 @@ TranslatingPort::memsetBlob(Addr addr, uint8_t val, int size)
 bool
 TranslatingPort::tryWriteString(Addr addr, const char *str)
 {
-#if !FULL_SYSTEM
     uint8_t c;
 
     Addr vaddr = addr;
@@ -178,7 +171,6 @@ TranslatingPort::tryWriteString(Addr addr, const char *str)
         Port::writeBlob(paddr, &c, 1);
     } while (c);
 
-#endif
     return true;
 }
 
@@ -192,7 +184,6 @@ TranslatingPort::writeString(Addr addr, const char *str)
 bool
 TranslatingPort::tryReadString(std::string &str, Addr addr)
 {
-#if !FULL_SYSTEM
     uint8_t c;
 
     Addr vaddr = addr;
@@ -207,7 +198,6 @@ TranslatingPort::tryReadString(std::string &str, Addr addr)
         str += c;
     } while (c);
 
-#endif
     return true;
 }
 
diff --git a/src/mem/translating_port.hh b/src/mem/translating_port.hh
index ee0aea8df..dffcac766 100644
--- a/src/mem/translating_port.hh
+++ b/src/mem/translating_port.hh
@@ -35,8 +35,8 @@
 #include "config/full_system.hh"
 #include "mem/port.hh"
 
-#if !FULL_SYSTEM
 class PageTable;
+#if !FULL_SYSTEM
 class Process;
 #endif
 
@@ -50,8 +50,8 @@ class TranslatingPort : public FunctionalPort
     };
 
   private:
-#if !FULL_SYSTEM
     PageTable *pTable;
+#if !FULL_SYSTEM
     Process *process;
 #endif
     AllocType allocating;