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authorMatt Sinclair <mattdsinclair@gmail.com>2017-12-06 20:29:11 -0500
committerMatt Sinclair <mattdsinclair@gmail.com>2017-12-08 04:05:58 +0000
commitbd7eadb4670458044c7628dc67d94d50c3f7593d (patch)
treed56ccd3bea7765af275fdbfcdcdd6b4665775b2e /src
parent66a55ce3ffd42663981a54144cfca311502f22b6 (diff)
downloadgem5-bd7eadb4670458044c7628dc67d94d50c3f7593d.tar.xz
x86,misc: add additional info on faulting X86 instruction, fetched PC
Print faulting instruction for unmapped address panic in faults.cc and print extra info about corresponding fetched PC in base.cc. Change-Id: Id9e15d3e88df2ad6b809fb3cf9f6ae97e9e97e0f Reviewed-on: https://gem5-review.googlesource.com/6461 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/faults.cc11
-rw-r--r--src/cpu/simple/base.cc8
2 files changed, 14 insertions, 5 deletions
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 4198bcc7c..093926d36 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -44,6 +44,7 @@
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/isa_traits.hh"
+#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
@@ -161,7 +162,15 @@ namespace X86ISA
modeStr = "write";
else
modeStr = "read";
- panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
+
+ // print information about what we are panic'ing on
+ if (!inst) {
+ panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
+ } else {
+ panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s",
+ modeStr, addr, tc->pcState().pc(),
+ inst->disassemble(tc->pcState().pc(), debugSymbolTable));
+ }
}
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 5c8eba6ef..1f12afbf0 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -475,13 +475,13 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
SimpleThread* thread = t_info.thread;
Addr instAddr = thread->instAddr();
+ Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
// set up memory request for instruction fetch
- DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
+ DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
- Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
- req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
- instAddr);
+ req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
+ instMasterId(), instAddr);
}