MIPS: Format the register index constants like the other ISAs.

Also a few more style fixes.

14 files changed, 465 insertions, 455 deletions

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 6faab054f..815784388 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -178,18 +178,18 @@ void
 MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
 {
     // modify SRS Ctl - Save CSS, put ESS into CSS
-    StatusReg status = tc->readMiscReg(Status);
+    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
     if (status.exl != 1 && status.bev != 1) {
         // SRS Ctl is modified only if Status_EXL and Status_BEV are not set
-        SRSCtlReg srsCtl = tc->readMiscReg(SRSCtl);
+        SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
         srsCtl.pss = srsCtl.css;
         srsCtl.css = srsCtl.ess;
-        tc->setMiscRegNoEffect(SRSCtl, srsCtl);
+        tc->setMiscRegNoEffect(MISCREG_SRSCTL, srsCtl);
     }
 
     // set EXL bit (don't care if it is already set!)
     status.exl = 1;
-    tc->setMiscRegNoEffect(Status, status);
+    tc->setMiscRegNoEffect(MISCREG_STATUS, status);
 
     // write EPC
     // CHECK ME  or FIXME or FIX ME or POSSIBLE HACK
@@ -198,21 +198,21 @@ MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
             tc->readPC(), tc->readNextPC(), tc->readNextNPC());
     int bd = 0;
     if (tc->readPC() + sizeof(MachInst) != tc->readNextPC()) {
-        tc->setMiscRegNoEffect(EPC, tc->readPC() - sizeof(MachInst));
+        tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC() - sizeof(MachInst));
         // In the branch delay slot? set CAUSE_31
         bd = 1;
     } else {
-        tc->setMiscRegNoEffect(EPC, tc->readPC());
+        tc->setMiscRegNoEffect(MISCREG_EPC, tc->readPC());
         // In the branch delay slot? reset CAUSE_31
         bd = 0;
     }
 
     // Set Cause_EXCCODE field
-    CauseReg cause = tc->readMiscReg(Cause);
+    CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
     cause.excCode = excCode;
     cause.bd = bd;
     cause.ce = 0;
-    tc->setMiscRegNoEffect(Cause, cause);
+    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 }
 
 void
@@ -223,12 +223,12 @@ ArithmeticFault::invoke(ThreadContext *tc)
 
     // Set new PC
     Addr HandlerBase;
-    StatusReg status = tc->readMiscReg(Status);
+    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
     // Here, the handler is dependent on BEV, which is not modified by
     // setExceptionState()
     if (!status.bev) {
         // See MIPS ARM Vol 3, Revision 2, Page 38
-        HandlerBase = vect() + tc->readMiscReg(EBase);
+        HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     } else {
         HandlerBase = 0xBFC00200;
     }
@@ -240,12 +240,12 @@ StoreAddressErrorFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x5);
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -258,7 +258,7 @@ TrapFault::invoke(ThreadContext *tc)
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -270,7 +270,7 @@ BreakpointFault::invoke(ThreadContext *tc)
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -279,23 +279,23 @@ DtbInvalidFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
 
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
     entryHi.asid = entryHiAsid;
     entryHi.vpn2 = entryHiVPN2;
     entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(EntryHi, entryHi);
+    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
 
-    ContextReg context = tc->readMiscReg(Context);
+    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
     context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(Context, context);
+    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
     setExceptionState(tc, 0x3);
 
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -304,12 +304,12 @@ AddressErrorFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x4);
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -318,51 +318,51 @@ ItbInvalidFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x2);
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
     entryHi.asid = entryHiAsid;
     entryHi.vpn2 = entryHiVPN2;
     entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(EntryHi, entryHi);
+    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
 
-    ContextReg context = tc->readMiscReg(Context);
+    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
     context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(Context, context);
+    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
 
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase,tc);
     DPRINTF(MipsPRA, "Exception Handler At: %x , EPC set to %x\n",
-            HandlerBase, tc->readMiscReg(EPC));
+            HandlerBase, tc->readMiscReg(MISCREG_EPC));
 }
 
 void
 ItbRefillFault::invoke(ThreadContext *tc)
 {
-    DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), badVAddr);
+    DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
     Addr HandlerBase;
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
     entryHi.asid = entryHiAsid;
     entryHi.vpn2 = entryHiVPN2;
     entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(EntryHi, entryHi);
-    ContextReg context = tc->readMiscReg(Context);
+    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
+    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
     context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(Context, context);
+    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
 
-    StatusReg status = tc->readMiscReg(Status);
+    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
     // Since handler depends on EXL bit, must check EXL bit before setting it!!
     // See MIPS ARM Vol 3, Revision 2, Page 38
     if (status.exl == 1) {
         // Offset 0x180 - General Exception Vector
-        HandlerBase = vect() + tc->readMiscReg(EBase);
+        HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     } else {
         // Offset 0x000
-        HandlerBase = tc->readMiscReg(EBase);
+        HandlerBase = tc->readMiscReg(MISCREG_EBASE);
     }
 
     setExceptionState(tc, 0x2);
@@ -375,26 +375,26 @@ DtbRefillFault::invoke(ThreadContext *tc)
     // Set new PC
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     Addr HandlerBase;
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
     entryHi.asid = entryHiAsid;
     entryHi.vpn2 = entryHiVPN2;
     entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(EntryHi, entryHi);
+    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
 
-    ContextReg context = tc->readMiscReg(Context);
+    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
     context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(Context, context);
+    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
 
-    StatusReg status = tc->readMiscReg(Status);
+    StatusReg status = tc->readMiscReg(MISCREG_STATUS);
     // Since handler depends on EXL bit, must check EXL bit before setting it!!
     // See MIPS ARM Vol 3, Revision 2, Page 38
     if (status.exl) {
         // Offset 0x180 - General Exception Vector
-        HandlerBase = vect() + tc->readMiscReg(EBase);
+        HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     } else {
         // Offset 0x000
-        HandlerBase = tc->readMiscReg(EBase);
+        HandlerBase = tc->readMiscReg(MISCREG_EBASE);
     }
 
     setExceptionState(tc, 0x3);
@@ -406,21 +406,21 @@ void
 TLBModifiedFault::invoke(ThreadContext *tc)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
-    tc->setMiscRegNoEffect(BadVAddr, badVAddr);
-    EntryHiReg entryHi = tc->readMiscReg(EntryHi);
+    tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+    EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
     entryHi.asid = entryHiAsid;
     entryHi.vpn2 = entryHiVPN2;
     entryHi.vpn2x = entryHiVPN2X;
-    tc->setMiscRegNoEffect(EntryHi, entryHi);
+    tc->setMiscRegNoEffect(MISCREG_ENTRYHI, entryHi);
 
-    ContextReg context = tc->readMiscReg(Context);
+    ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
     context.badVPN2 = contextBadVPN2;
-    tc->setMiscRegNoEffect(Context, context);
+    tc->setMiscRegNoEffect(MISCREG_CONTEXT, context);
 
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setExceptionState(tc, 0x1);
     setHandlerPC(HandlerBase, tc);
 
@@ -435,7 +435,7 @@ SystemCallFault::invoke(ThreadContext *tc)
     // Set new PC
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 }
 
@@ -447,13 +447,13 @@ InterruptFault::invoke(ThreadContext *tc)
     setExceptionState(tc, 0x0A);
     Addr HandlerBase;
 
-    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
     if (cause.iv) {
         // Offset 200 for release 2
-        HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(EBase);
+        HandlerBase = 0x20 + vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
     } else {
         //Ofset at 180 for release 1
-        HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
+        HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
     }
 
     setHandlerPC(HandlerBase, tc);
@@ -475,9 +475,9 @@ ResetFault::invoke(ThreadContext *tc)
 #endif
 
     // Set Coprocessor 1 (Floating Point) To Usable
-    StatusReg status = tc->readMiscRegNoEffect(Status);
+    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
     status.cu.cu1 = 1;
-    tc->setMiscReg(Status, status);
+    tc->setMiscReg(MISCREG_STATUS, status);
 }
 
 void
@@ -488,7 +488,7 @@ ReservedInstructionFault::invoke(ThreadContext *tc)
     setExceptionState(tc, 0x0A);
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscRegNoEffect(EBase);
+    HandlerBase = vect() + tc->readMiscRegNoEffect(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 #else
     panic("%s encountered.\n", name());
@@ -517,13 +517,13 @@ CoprocessorUnusableFault::invoke(ThreadContext *tc)
     setExceptionState(tc, 0xb);
     // The ID of the coprocessor causing the exception is stored in
     // CoprocessorUnusableFault::coProcID
-    CauseReg cause = tc->readMiscReg(Cause);
+    CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
     cause.ce = coProcID;
-    tc->setMiscRegNoEffect(Cause, cause);
+    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 
     Addr HandlerBase;
     // Offset 0x180 - General Exception Vector
-    HandlerBase = vect() + tc->readMiscReg(EBase);
+    HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
     setHandlerPC(HandlerBase, tc);
 
 #else
diff --git a/src/arch/mips/interrupts.cc b/src/arch/mips/interrupts.cc
index 4b1f37856..096aa628f 100755
--- a/src/arch/mips/interrupts.cc
+++ b/src/arch/mips/interrupts.cc
@@ -42,15 +42,15 @@ namespace MipsISA
 
 static inline uint8_t
 getCauseIP(ThreadContext *tc) {
-    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
     return cause.ip;
 }
 
 static inline void
 setCauseIP(ThreadContext *tc, uint8_t val) {
-    CauseReg cause = tc->readMiscRegNoEffect(Cause);
+    CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
     cause.ip = val;
-    tc->setMiscRegNoEffect(Cause, cause);
+    tc->setMiscRegNoEffect(MISCREG_CAUSE, cause);
 }
 
 void
@@ -111,14 +111,14 @@ Interrupts::getInterrupt(ThreadContext * tc)
     DPRINTF(Interrupt, "Interrupts getInterrupt\n");
 
     //Check if there are any outstanding interrupts
-    StatusReg status = tc->readMiscRegNoEffect(Status);
+    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
     // Interrupts must be enabled, error level must be 0 or interrupts
     // inhibited, and exception level must be 0 or interrupts inhibited
     if ((status.ie == 1) && (status.erl == 0) && (status.exl == 0)) {
         // Software interrupts & hardware interrupts are handled in software.
         // So if any interrupt that isn't masked is detected, jump to interrupt
         // handler
-        CauseReg cause = tc->readMiscRegNoEffect(Cause);
+        CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
         if (status.im && cause.ip) {
             DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
                     (unsigned)status.im, (unsigned)cause.ip);
@@ -132,8 +132,8 @@ Interrupts::getInterrupt(ThreadContext * tc)
 bool
 Interrupts::onCpuTimerInterrupt(ThreadContext * tc) const
 {
-    MiscReg compare = tc->readMiscRegNoEffect(Compare);
-    MiscReg count = tc->readMiscRegNoEffect(Count);
+    MiscReg compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
+    MiscReg count = tc->readMiscRegNoEffect(MISCREG_COUNT);
     if (compare == count && count != 0)
         return true;
     return false;
@@ -153,7 +153,7 @@ Interrupts::interruptsPending(ThreadContext *tc) const
     if (onCpuTimerInterrupt(tc)) {
         DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
         //determine timer interrupt IP #
-        IntCtlReg intCtl = tc->readMiscRegNoEffect(IntCtl);
+        IntCtlReg intCtl = tc->readMiscRegNoEffect(MISCREG_INTCTL);
         uint8_t intStatus = getCauseIP(tc);
         intStatus |= 1 << intCtl.ipti;
         setCauseIP(tc, intStatus);
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 6ef6f9f41..3c8c9a986 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -129,10 +129,14 @@ void
 ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
 {
     // Initialize all Per-VPE regs
-    uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask,
-                                VPESchedule, VPEScheFBack, VPEOpt, SRSConf0,
-                                SRSConf1, SRSConf2, SRSConf3, SRSConf4,
-                                EBase
+    uint32_t per_vpe_regs[] = { MISCREG_VPE_CONTROL,
+                                MISCREG_VPE_CONF0, MISCREG_VPE_CONF1,
+                                MISCREG_YQMASK,
+                                MISCREG_VPE_SCHEDULE, MISCREG_VPE_SCHEFBACK,
+                                MISCREG_VPE_OPT, MISCREG_SRS_CONF0,
+                                MISCREG_SRS_CONF1, MISCREG_SRS_CONF2,
+                                MISCREG_SRS_CONF3, MISCREG_SRS_CONF4,
+                                MISCREG_EBASE
                               };
     uint32_t num_vpe_regs = sizeof(per_vpe_regs) / 4;
     for (int i = 0; i < num_vpe_regs; i++) {
@@ -143,9 +147,12 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
     }
 
     // Initialize all Per-TC regs
-    uint32_t per_tc_regs[] = { Status, TCStatus, TCBind, TCRestart, TCHalt,
-                               TCContext, TCSchedule, TCScheFBack, Debug,
-                               LLAddr
+    uint32_t per_tc_regs[] = { MISCREG_STATUS,
+                               MISCREG_TC_STATUS, MISCREG_TC_BIND,
+                               MISCREG_TC_RESTART, MISCREG_TC_HALT,
+                               MISCREG_TC_CONTEXT, MISCREG_TC_SCHEDULE,
+                               MISCREG_TC_SCHEFBACK,
+                               MISCREG_DEBUG, MISCREG_LLADDR
                              };
     uint32_t num_tc_regs = sizeof(per_tc_regs) /  4;
 
@@ -181,34 +188,34 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     // ===================================================
     DPRINTF(MipsPRA, "Initializing CP0 State.... ");
 
-    PRIdReg procId = readMiscRegNoEffect(PRId);
+    PRIdReg procId = readMiscRegNoEffect(MISCREG_PRID);
     procId.coOp = cp.CP0_PRId_CompanyOptions;
     procId.coId = cp.CP0_PRId_CompanyID;
     procId.procId = cp.CP0_PRId_ProcessorID;
     procId.rev = cp.CP0_PRId_Revision;
-    setMiscRegNoEffect(PRId, procId);
+    setMiscRegNoEffect(MISCREG_PRID, procId);
 
     // Now, create Write Mask for ProcID register
-    MiscReg ProcID_Mask = 0; // Read-Only register
-    replaceBits(ProcID_Mask, 0, 32, 0);
-    setRegMask(PRId, ProcID_Mask);
+    MiscReg procIDMask = 0; // Read-Only register
+    replaceBits(procIDMask, 0, 32, 0);
+    setRegMask(MISCREG_PRID, procIDMask);
 
     // Config
-    ConfigReg cfg = readMiscRegNoEffect(Config);
+    ConfigReg cfg = readMiscRegNoEffect(MISCREG_CONFIG);
     cfg.be = cp.CP0_Config_BE;
     cfg.at = cp.CP0_Config_AT;
     cfg.ar = cp.CP0_Config_AR;
     cfg.mt = cp.CP0_Config_MT;
     cfg.vi = cp.CP0_Config_VI;
     cfg.m = 1;
-    setMiscRegNoEffect(Config, cfg);
+    setMiscRegNoEffect(MISCREG_CONFIG, cfg);
     // Now, create Write Mask for Config register
     MiscReg cfg_Mask = 0x7FFF0007;
     replaceBits(cfg_Mask, 0, 32, 0);
-    setRegMask(Config, cfg_Mask);
+    setRegMask(MISCREG_CONFIG, cfg_Mask);
 
     // Config1
-    Config1Reg cfg1 = readMiscRegNoEffect(Config1);
+    Config1Reg cfg1 = readMiscRegNoEffect(MISCREG_CONFIG1);
     cfg1.mmuSize = cp.CP0_Config1_MMU;
     cfg1.is = cp.CP0_Config1_IS;
     cfg1.il = cp.CP0_Config1_IL;
@@ -223,14 +230,14 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     cfg1.c2 = cp.CP0_Config1_C2;
     cfg1.pc = cp.CP0_Config1_PC;
     cfg1.m = cp.CP0_Config1_M;
-    setMiscRegNoEffect(Config1, cfg1);
+    setMiscRegNoEffect(MISCREG_CONFIG1, cfg1);
     // Now, create Write Mask for Config register
     MiscReg cfg1_Mask = 0; // Read Only Register
     replaceBits(cfg1_Mask, 0, 32, 0);
-    setRegMask(Config1, cfg1_Mask);
+    setRegMask(MISCREG_CONFIG1, cfg1_Mask);
 
     // Config2
-    Config2Reg cfg2 = readMiscRegNoEffect(Config2);
+    Config2Reg cfg2 = readMiscRegNoEffect(MISCREG_CONFIG2);
     cfg2.tu = cp.CP0_Config2_TU;
     cfg2.ts = cp.CP0_Config2_TS;
     cfg2.tl = cp.CP0_Config2_TL;
@@ -240,14 +247,14 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     cfg2.sl = cp.CP0_Config2_SL;
     cfg2.sa = cp.CP0_Config2_SA;
     cfg2.m = cp.CP0_Config2_M;
-    setMiscRegNoEffect(Config2, cfg2);
+    setMiscRegNoEffect(MISCREG_CONFIG2, cfg2);
     // Now, create Write Mask for Config register
     MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
     replaceBits(cfg2_Mask, 0, 32, 0);
-    setRegMask(Config2, cfg2_Mask);
+    setRegMask(MISCREG_CONFIG2, cfg2_Mask);
 
     // Config3
-    Config3Reg cfg3 = readMiscRegNoEffect(Config3);
+    Config3Reg cfg3 = readMiscRegNoEffect(MISCREG_CONFIG3);
     cfg3.dspp = cp.CP0_Config3_DSPP;
     cfg3.lpa = cp.CP0_Config3_LPA;
     cfg3.veic = cp.CP0_Config3_VEIC;
@@ -256,79 +263,79 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     cfg3.mt = cp.CP0_Config3_MT;
     cfg3.sm = cp.CP0_Config3_SM;
     cfg3.tl = cp.CP0_Config3_TL;
-    setMiscRegNoEffect(Config3, cfg3);
+    setMiscRegNoEffect(MISCREG_CONFIG3, cfg3);
     // Now, create Write Mask for Config register
     MiscReg cfg3_Mask = 0; // Read Only Register
     replaceBits(cfg3_Mask, 0, 32, 0);
-    setRegMask(Config3, cfg3_Mask);
+    setRegMask(MISCREG_CONFIG3, cfg3_Mask);
 
     // EBase - CPUNum
-    EBaseReg eBase = readMiscRegNoEffect(EBase);
+    EBaseReg eBase = readMiscRegNoEffect(MISCREG_EBASE);
     eBase.cpuNum = cp.CP0_EBase_CPUNum;
     replaceBits(eBase, 31, 31, 1);
-    setMiscRegNoEffect(EBase, eBase);
+    setMiscRegNoEffect(MISCREG_EBASE, eBase);
     // Now, create Write Mask for Config register
     MiscReg EB_Mask = 0x3FFFF000;// Except Exception Base, the
                                  // entire register is read only
     replaceBits(EB_Mask, 0, 32, 0);
-    setRegMask(EBase, EB_Mask);
+    setRegMask(MISCREG_EBASE, EB_Mask);
 
     // SRS Control - HSS (Highest Shadow Set)
-    SRSCtlReg scsCtl = readMiscRegNoEffect(SRSCtl);
+    SRSCtlReg scsCtl = readMiscRegNoEffect(MISCREG_SRSCTL);
     scsCtl.hss = cp.CP0_SrsCtl_HSS;
-    setMiscRegNoEffect(SRSCtl, scsCtl);
+    setMiscRegNoEffect(MISCREG_SRSCTL, scsCtl);
     // Now, create Write Mask for the SRS Ctl register
     MiscReg SC_Mask = 0x0000F3C0;
     replaceBits(SC_Mask, 0, 32, 0);
-    setRegMask(SRSCtl, SC_Mask);
+    setRegMask(MISCREG_SRSCTL, SC_Mask);
 
     // IntCtl - IPTI, IPPCI
-    IntCtlReg intCtl = readMiscRegNoEffect(IntCtl);
+    IntCtlReg intCtl = readMiscRegNoEffect(MISCREG_INTCTL);
     intCtl.ipti = cp.CP0_IntCtl_IPTI;
     intCtl.ippci = cp.CP0_IntCtl_IPPCI;
-    setMiscRegNoEffect(IntCtl, intCtl);
+    setMiscRegNoEffect(MISCREG_INTCTL, intCtl);
     // Now, create Write Mask for the IntCtl register
     MiscReg IC_Mask = 0x000003E0;
     replaceBits(IC_Mask, 0, 32, 0);
-    setRegMask(IntCtl, IC_Mask);
+    setRegMask(MISCREG_INTCTL, IC_Mask);
 
     // Watch Hi - M - FIXME (More than 1 Watch register)
-    WatchHiReg watchHi = readMiscRegNoEffect(WatchHi0);
+    WatchHiReg watchHi = readMiscRegNoEffect(MISCREG_WATCHHI0);
     watchHi.m = cp.CP0_WatchHi_M;
-    setMiscRegNoEffect(WatchHi0, watchHi);
+    setMiscRegNoEffect(MISCREG_WATCHHI0, watchHi);
     // Now, create Write Mask for the IntCtl register
     MiscReg wh_Mask = 0x7FFF0FFF;
     replaceBits(wh_Mask, 0, 32, 0);
-    setRegMask(WatchHi0, wh_Mask);
+    setRegMask(MISCREG_WATCHHI0, wh_Mask);
 
     // Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
-    PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(PerfCnt0);
+    PerfCntCtlReg perfCntCtl = readMiscRegNoEffect(MISCREG_PERFCNT0);
     perfCntCtl.m = cp.CP0_PerfCtr_M;
     perfCntCtl.w = cp.CP0_PerfCtr_W;
-    setMiscRegNoEffect(PerfCnt0, perfCntCtl);
+    setMiscRegNoEffect(MISCREG_PERFCNT0, perfCntCtl);
     // Now, create Write Mask for the IntCtl register
     MiscReg pc_Mask = 0x00007FF;
     replaceBits(pc_Mask, 0, 32, 0);
-    setRegMask(PerfCnt0, pc_Mask);
+    setRegMask(MISCREG_PERFCNT0, pc_Mask);
 
     // Random
-    setMiscRegNoEffect(CP0_Random, 63);
+    setMiscRegNoEffect(MISCREG_CP0_RANDOM, 63);
     // Now, create Write Mask for the IntCtl register
     MiscReg random_Mask = 0;
     replaceBits(random_Mask, 0, 32, 0);
-    setRegMask(CP0_Random, random_Mask);
+    setRegMask(MISCREG_CP0_RANDOM, random_Mask);
 
     // PageGrain
-    PageGrainReg pageGrain = readMiscRegNoEffect(PageGrain);
+    PageGrainReg pageGrain = readMiscRegNoEffect(MISCREG_PAGEGRAIN);
     pageGrain.esp = cp.CP0_Config3_SP;
-    setMiscRegNoEffect(PageGrain, pageGrain);
+    setMiscRegNoEffect(MISCREG_PAGEGRAIN, pageGrain);
     // Now, create Write Mask for the IntCtl register
     MiscReg pg_Mask = 0x10000000;
     replaceBits(pg_Mask, 0, 32, 0);
-    setRegMask(PageGrain, pg_Mask);
+    setRegMask(MISCREG_PAGEGRAIN, pg_Mask);
 
     // Status
-    StatusReg status = readMiscRegNoEffect(Status);
+    StatusReg status = readMiscRegNoEffect(MISCREG_STATUS);
     // Only CU0 and IE are modified on a reset - everything else needs
     // to be controlled on a per CPU model basis
 
@@ -340,91 +347,90 @@ ISA::reset(std::string core_name, ThreadID num_threads,
     // Enable BEV bit on a reset
     status.bev = 1;
 
-    setMiscRegNoEffect(Status, status);
+    setMiscRegNoEffect(MISCREG_STATUS, status);
     // Now, create Write Mask for the Status register
     MiscReg stat_Mask = 0xFF78FF17;
     replaceBits(stat_Mask, 0, 32, 0);
-    setRegMask(Status, stat_Mask);
+    setRegMask(MISCREG_STATUS, stat_Mask);
 
 
     // MVPConf0
-    MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
+    MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
     mvpConf0.tca = 1;
     mvpConf0.pvpe = num_vpes - 1;
     mvpConf0.ptc = num_threads - 1;
-    setMiscRegNoEffect(MVPConf0, mvpConf0);
+    setMiscRegNoEffect(MISCREG_MVP_CONF0, mvpConf0);
 
     // VPEConf0
-    VPEConf0Reg vpeConf0 = readMiscRegNoEffect(VPEConf0);
+    VPEConf0Reg vpeConf0 = readMiscRegNoEffect(MISCREG_VPE_CONF0);
     vpeConf0.mvp = 1;
-    setMiscRegNoEffect(VPEConf0, vpeConf0);
+    setMiscRegNoEffect(MISCREG_VPE_CONF0, vpeConf0);
 
     // TCBind
     for (ThreadID tid = 0; tid < num_threads; tid++) {
-        TCBindReg tcBind = readMiscRegNoEffect(TCBind, tid);
+        TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
         tcBind.curTC = tid;
-        setMiscRegNoEffect(TCBind, tcBind, tid);
+        setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
     }
     // TCHalt
-    TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt);
+    TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT);
     tcHalt.h = 0;
-    setMiscRegNoEffect(TCHalt, tcHalt);
+    setMiscRegNoEffect(MISCREG_TC_HALT, tcHalt);
 
     // TCStatus
     // Set TCStatus Activated to 1 for the initial thread that is running
-    TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus);
+    TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS);
     tcStatus.a = 1;
-    setMiscRegNoEffect(TCStatus, tcStatus);
+    setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
 
     // Set Dynamically Allocatable bit to 1 for all other threads
     for (ThreadID tid = 1; tid < num_threads; tid++) {
-        tcStatus = readMiscRegNoEffect(TCStatus, tid);
+        tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
         tcStatus.da = 1;
-        setMiscRegNoEffect(TCStatus, tcStatus, tid);
+        setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
     }
 
 
-    MiscReg Mask = 0x7FFFFFFF;
+    MiscReg mask = 0x7FFFFFFF;
 
     // Now, create Write Mask for the Index register
-    replaceBits(Mask, 0, 32, 0);
-    setRegMask(Index, Mask);
+    replaceBits(mask, 0, 32, 0);
+    setRegMask(MISCREG_INDEX, mask);
 
-    Mask = 0x3FFFFFFF;
-    replaceBits(Mask, 0, 32, 0);
-    setRegMask(EntryLo0, Mask);
-    setRegMask(EntryLo1, Mask);
+    mask = 0x3FFFFFFF;
+    replaceBits(mask, 0, 32, 0);
+    setRegMask(MISCREG_ENTRYLO0, mask);
+    setRegMask(MISCREG_ENTRYLO1, mask);
 
-    Mask = 0xFF800000;
-    replaceBits(Mask, 0, 32, 0);
-    setRegMask(Context, Mask);
+    mask = 0xFF800000;
+    replaceBits(mask, 0, 32, 0);
+    setRegMask(MISCREG_CONTEXT, mask);
 
-    Mask = 0x1FFFF800;
-    replaceBits(Mask, 0, 32, 0);
-    setRegMask(PageMask, Mask);
+    mask = 0x1FFFF800;
+    replaceBits(mask, 0, 32, 0);
+    setRegMask(MISCREG_PAGEMASK, mask);
 
-    Mask = 0x0;
-    replaceBits(Mask, 0, 32, 0);
-    setRegMask(BadVAddr, Mask);
-    setRegMask(LLAddr, Mask);
+    mask = 0x0;
+    replaceBits(mask, 0, 32, 0);
+    setRegMask(MISCREG_BADVADDR, mask);
+    setRegMask(MISCREG_LLADDR, mask);
 
-    Mask = 0x08C00300;
-    replaceBits(Mask, 0, 32, 0);
-    setRegMask(Cause, Mask);
+    mask = 0x08C00300;
+    replaceBits(mask, 0, 32, 0);
+    setRegMask(MISCREG_CAUSE, mask);
 
 }
 
 inline unsigned
 ISA::getVPENum(ThreadID tid)
 {
-    TCBindReg tcBind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
+    TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
     return tcBind.curVPE;
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    int misc_reg = reg_idx - Ctrl_Base_DepTag;
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
@@ -437,9 +443,8 @@ ISA::readMiscRegNoEffect(int reg_idx, ThreadID tid)
 //       Status to TCStatus depending on current thread
 //template <class TC>
 MiscReg
-ISA::readMiscReg(int reg_idx, ThreadContext *tc,  ThreadID tid)
+ISA::readMiscReg(int misc_reg, ThreadContext *tc,  ThreadID tid)
 {
-    int misc_reg = reg_idx - Ctrl_Base_DepTag;
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA,
@@ -451,9 +456,8 @@ ISA::readMiscReg(int reg_idx, ThreadContext *tc,  ThreadID tid)
 }
 
 void
-ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    int misc_reg = reg_idx - Ctrl_Base_DepTag;
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA,
@@ -465,10 +469,8 @@ ISA::setMiscRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
 }
 
 void
-ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid)
+ISA::setRegMask(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-  //  return;
-  int misc_reg = reg_idx - Ctrl_Base_DepTag;
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
     DPRINTF(MipsPRA,
@@ -482,10 +484,9 @@ ISA::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid)
 // be overwritten. Make sure to handle those particular registers
 // with care!
 void
-ISA::setMiscReg(int reg_idx, const MiscReg &val,
+ISA::setMiscReg(int misc_reg, const MiscReg &val,
                     ThreadContext *tc, ThreadID tid)
 {
-    int misc_reg = reg_idx - Ctrl_Base_DepTag;
     int reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
 
@@ -546,12 +547,12 @@ ISA::updateCPU()
     // EVALUATE CP0 STATE FOR MIPS MT
     //
     ///////////////////////////////////////////////////////////////////
-    MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MVPConf0);
+    MVPConf0Reg mvpConf0 = readMiscRegNoEffect(MISCREG_MVP_CONF0);
     ThreadID num_threads = mvpConf0.ptc + 1;
 
     for (ThreadID tid = 0; tid < num_threads; tid++) {
-        TCStatusReg tcStatus = readMiscRegNoEffect(TCStatus, tid);
-        TCHaltReg tcHalt = readMiscRegNoEffect(TCHalt, tid);
+        TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
+        TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
 
         //@todo: add vpe/mt check here thru mvpcontrol & vpecontrol regs
         if (tcHalt.h == 1 || tcStatus.a == 0)  {
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 60bc15513..f8cdb920b 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -406,19 +406,19 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x1: decode SEL {
                             0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
                             0x1: decode RT {
-                                0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
-                                0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
-                                0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
-                                0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
-                                0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
-                                0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
-                                0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
-                                0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
-                                0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
-                                0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
-                                0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
-                                0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
-                                0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
+                                0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }});
+                                0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }});
+                                0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }});
+                                0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }});
+                                0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }});
+                                0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }});
+                                0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }});
+                                0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }});
+                                0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }});
+                                0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }});
+                                0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }});
+                                0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }});
+                                0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }});
                                default: CP0Unimpl::unknown();
                             }
                             0x2: decode MT_H {
@@ -429,12 +429,12 @@ decode OPCODE_HI default Unknown::unknown() {
                                                                              FP_Base_DepTag);
                                            }});
                                }
-                            0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
+                            0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR +
                                                                             FP_Base_DepTag);
                                           switch (RT)
                                           {
                                                case 0:
-                                                 data = xc->readRegOtherThread(MipsISA::FIR +
+                                                 data = xc->readRegOtherThread(FLOATREG_FIR +
                                                                                Ctrl_Base_DepTag);
                                                  break;
                                                case 25:
@@ -469,41 +469,41 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x1: decode SEL {
                             0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
                             0x1: decode RT {
-                                0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
+                                0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt);
                                                 }});
-                                0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
+                                0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0,
                                                                          Rt);
                                                 }});
-                                0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
+                                0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0,
                                                                           Rt);
                                                  }});
-                                0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
+                                0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1,
                                                                          Rt);
                                                 }});
-                                0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
+                                0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1,
                                                                          Rt);
                                                 }});
-                                0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
+                                0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1,
                                                                           Rt);
                                                  }});
-                                0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
+                                0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2,
                                                                          Rt);
                                                 }});
-                                0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
+                                0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2,
                                                                          Rt);
                                                 }});
-                                0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
+                                0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2,
                                                                            Rt);
                                                   }});
-                                0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
+                                0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3,
                                                                           Rt);
                                                  }});
-                                0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
+                                0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3,
                                                                           Rt);
                                                  }});
-                                0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
+                                0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt);
                                                   }});
-                                0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
+                                0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }});
                                default: CP0Unimpl::unknown();
 
                             }
@@ -546,7 +546,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                               panic("FP Control Value (%d) Not Available. Ignoring Access to"
                                                     "Floating Control Status Register", FS);
                                           }
-                                          xc->setRegOtherThread(FCSR, data);
+                                          xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
                                        }});
                                default: CP0Unimpl::unknown();
                         }
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index c8eddb1ad..cb5b4372f 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -180,12 +180,12 @@ output exec {{
 #if !FULL_SYSTEM
             return true;
 #else
-          MiscReg Stat = xc->readMiscReg(MipsISA::Status);
+          MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
           switch(cop_num)
             {
             case 0:
               {
-                  MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
+                  MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
                   if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
                      && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
                      && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
@@ -216,8 +216,8 @@ output exec {{
         bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
         {
 #if FULL_SYSTEM
-          MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
-          MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
+          MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS);
+          MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG);
           if((Stat & 0x10000006) == 0  // EXL, ERL or CU0 set, CP0 accessible
                  && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
                  && (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
@@ -232,7 +232,7 @@ output exec {{
         bool isMMUTLB(%(CPU_exec_context)s *xc)
         {
 #if FULL_SYSTEM
-          if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
+          if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80)
             return true;
 #endif
           return false;
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 1874d37b2..7d16b4162 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
     bool isDspEnabled(%(CPU_exec_context)s *xc)
     {
 #if FULL_SYSTEM
-        if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 )
+        if( bits( xc->readMiscReg(MISCREG_STATUS), 24, 24 ) == 0 )
             return false;
 #else
         //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n");
@@ -156,7 +156,7 @@ output exec {{
     bool isDspPresent(%(CPU_exec_context)s *xc)
     {
 #if FULL_SYSTEM
-        if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 )
+        if( bits( xc->readMiscReg(MISCREG_CONFIG3), 10, 10 ) == 0 )
             return false;
 #else
         //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n");
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 52fcd0724..72d87f997 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -135,12 +135,13 @@ output exec {{
                 cpu->setFloatRegOperandBits(inst, 0, mips_nan);
 
                 //Read FCSR from FloatRegFile
-                uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
+                uint32_t fcsr_bits =
+                    cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
 
                 uint32_t new_fcsr = genInvalidVector(fcsr_bits);
 
                 //Write FCSR from FloatRegFile
-                cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
+                cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr);
 
                 if (traceData) { traceData->setData(mips_nan); }
                 return true;
@@ -153,13 +154,13 @@ output exec {{
         fpResetCauseBits(%(CPU_exec_context)s *cpu)
         {
             //Read FCSR from FloatRegFile
-            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
+            uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR);
 
             // TODO: Use utility function here
             fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
 
             //Write FCSR from FloatRegFile
-            cpu->tcBase()->setFloatRegBits(FCSR, fcsr);
+            cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr);
         }
 }};
 
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 4f2d33709..9d354c46a 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -90,16 +90,16 @@ output exec {{
             TCBindReg &tc_bind, VPEControlReg &vpe_control,
             MVPConf0Reg &mvp_conf0)
     {
-        vpe_conf0 = xc->readMiscReg(VPEConf0);
-        tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
-        tc_bind = xc->readMiscReg(TCBind);
-        vpe_control = xc->readMiscReg(VPEControl);
-        mvp_conf0 = xc->readMiscReg(MVPConf0);
+        vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0);
+        tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag);
+        tc_bind = xc->readMiscReg(MISCREG_TC_BIND);
+        vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL);
+        mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0);
     }
 
     void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3)
     {
-        config3 = xc->readMiscReg(Config3);
+        config3 = xc->readMiscReg(MISCREG_CONFIG3);
     }
 }};
 
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 1af8857cc..50726cd30 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -56,29 +56,29 @@ def operands {{
     'R2':  ('IntReg', 'uw','2', 'IsInteger', 5),
 
     #Special Integer Reg operands
-    'LO0':  ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
-    'HI0':  ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
+    'LO0':  ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
+    'HI0':  ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
 
     #Bitfield-dependent HI/LO Register Access
-    'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
-    'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
-    'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
-    'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
+    'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
+    'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
+    'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
+    'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
 
     #DSP Special Purpose Integer Operands
-    'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
-    'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
-    'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
-    'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
-    'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
-    'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
-    'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
-    'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
-    'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
-    'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
-    'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
-    'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
-    'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
+    'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
+    'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
+    'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
+    'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
+    'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
+    'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
+    'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
+    'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
+    'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
+    'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
+    'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
+    'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
+    'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
 
     #Floating Point Reg Operands
     'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
@@ -87,11 +87,11 @@ def operands {{
     'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
 
     #Special Purpose Floating Point Control Reg Operands
-    'FIR':  ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
-    'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
-    'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
-    'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
-    'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
+    'FIR':  ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
+    'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
+    'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
+    'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
+    'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
 
     #Operands For Paired Singles FP Operations
     'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
@@ -104,44 +104,45 @@ def operands {{
     'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
 
     #Status Control Reg
-    'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
+    'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
 
     #LL Flag
-    'LLFlag': ('ControlReg', 'uw', 'MipsISA::LLFlag', None, 1),
+    'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
 
     # Index Register
-    'Index':('ControlReg','uw','MipsISA::Index',None,1),
+    'Index':('ControlReg','uw','MISCREG_INDEX',None,1),
 
 
     'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
 
     #MT Control Regs
-    'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
-    'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
-    'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
-    'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
-    'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
-    'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
-    'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
-    'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
+    'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
+    'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
+    'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
+    'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
+    'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
+    'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
+    'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
+    'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
 
     #CP0 Control Regs
-    'EntryHi': ('ControlReg','uw', 'MipsISA::EntryHi',None,1),
-    'EntryLo0': ('ControlReg','uw', 'MipsISA::EntryLo0',None,1),
-    'EntryLo1': ('ControlReg','uw', 'MipsISA::EntryLo1',None,1),
-    'PageMask': ('ControlReg','uw', 'MipsISA::PageMask',None,1),
-    'Random': ('ControlReg','uw', 'MipsISA::CP0_Random',None,1),
-    'ErrorEPC': ('ControlReg','uw', 'MipsISA::ErrorEPC',None,1),
-    'EPC': ('ControlReg','uw', 'MipsISA::EPC',None,1),
-    'DEPC': ('ControlReg','uw', 'MipsISA::DEPC',None,1),
-    'SRSCtl': ('ControlReg','uw', 'MipsISA::SRSCtl',None,1),
-    'Config': ('ControlReg','uw', 'MipsISA::Config',None,1),
-    'Config3': ('ControlReg','uw', 'MipsISA::Config3',None,1),
-    'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1),
-    'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1),
-    'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1),
-    'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1),
-    'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1),
+    'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
+    'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
+    'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
+    'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
+    'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
+    'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
+    'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
+    'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
+    'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
+    'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
+    'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
+    'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
+    'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
+    'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
+    'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
+    'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
+    'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
 
     #Memory Operand
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 3c81bc249..2722ce8d2 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -50,8 +50,8 @@ template <class XC>
 inline void
 handleLockedRead(XC *xc, Request *req)
 {
-    xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
-    xc->setMiscRegNoEffect(LLFlag, true);
+    xc->setMiscRegNoEffect(MISCREG_LLADDR, req->getPaddr() & ~0xf);
+    xc->setMiscRegNoEffect(MISCREG_LLADDR, true);
     DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link"
                   " Address set to %x.\n",
             req->threadId(), req->getPaddr() & ~0xf);
@@ -67,14 +67,14 @@ handleLockedWrite(XC *xc, Request *req)
         req->setExtraData(2);
     } else {
         // standard store conditional
-        bool lock_flag = xc->readMiscRegNoEffect(LLFlag);
-        Addr lock_addr = xc->readMiscRegNoEffect(LLAddr);
+        bool lock_flag = xc->readMiscRegNoEffect(MISCREG_LLFLAG);
+        Addr lock_addr = xc->readMiscRegNoEffect(MISCREG_LLADDR);
 
         if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
             // Lock flag not set or addr mismatch in CPU;
             // don't even bother sending to memory system
             req->setExtraData(0);
-            xc->setMiscRegNoEffect(LLFlag, false);
+            xc->setMiscRegNoEffect(MISCREG_LLFLAG, false);
 
             // the rest of this code is not architectural;
             // it's just a debugging aid to help detect
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index a6363e191..3cb81c201 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -55,7 +55,7 @@ template <class TC>
 inline unsigned
 getVirtProcNum(TC *tc)
 {
-    TCBindReg tcbind = tc->readMiscRegNoEffect(TCBind);
+    TCBindReg tcbind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
     return tcbind.curVPE;
 }
 
@@ -63,7 +63,7 @@ template <class TC>
 inline unsigned
 getTargetThread(TC *tc)
 {
-    VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(VPEControl);
+    VPEControlReg vpeCtrl = tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
     return vpeCtrl.targTC;
 }
 
@@ -77,7 +77,7 @@ haltThread(TC *tc)
         // Save last known PC in TCRestart
         // @TODO: Needs to check if this is a branch and if so,
         // take previous instruction
-        tc->setMiscReg(TCRestart, tc->readNextPC());
+        tc->setMiscReg(MISCREG_TC_RESTART, tc->readNextPC());
 
         warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
                 curTick, tc->threadId(), tc->getCpuPtr()->name(),
@@ -91,7 +91,7 @@ restoreThread(TC *tc)
 {
     if (tc->status() != TC::Active) {
         // Restore PC from TCRestart
-        IntReg pc = tc->readMiscRegNoEffect(TCRestart);
+        IntReg pc = tc->readMiscRegNoEffect(MISCREG_TC_RESTART);
 
         // TODO: SET PC WITH AN EVENT INSTEAD OF INSTANTANEOUSLY
         tc->setPC(pc);
@@ -109,31 +109,33 @@ template <class TC>
 void
 forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
 {
-    MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MVPConf0);
+    MVPConf0Reg mvpConf = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
     int num_threads = mvpConf.ptc + 1;
 
     int success = 0;
     for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
         TCBindReg tidTCBind =
-            tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid);
-        TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind);
+            tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag, tid);
+        TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
 
         if (tidTCBind.curVPE = tcBind.curVPE) {
 
             TCStatusReg tidTCStatus =
-                tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag,tid);
+                tc->readRegOtherThread(MISCREG_TC_STATUS +
+                                       Ctrl_Base_DepTag,tid);
 
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag,tid);
+                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,tid);
 
             if (tidTCStatus.da == 1 && tidTCHalt.h == 0 &&
                 tidTCStatus.a == 0 && success == 0) {
 
-                tc->setRegOtherThread(TCRestart + Ctrl_Base_DepTag, Rs, tid);
+                tc->setRegOtherThread(MISCREG_TC_RESTART +
+                                      Ctrl_Base_DepTag, Rs, tid);
                 tc->setRegOtherThread(Rd_bits, Rt, tid);
 
-                StatusReg status = tc->readMiscReg(Status);
-                TCStatusReg tcStatus = tc->readMiscReg(TCStatus);
+                StatusReg status = tc->readMiscReg(MISCREG_STATUS);
+                TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS);
 
                 // Set Run-State to Running
                 tidTCStatus.rnst = 0;
@@ -149,7 +151,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
                 tidTCStatus.asid = tcStatus.asid;
 
                 // Write Status Register
-                tc->setRegOtherThread(TCStatus + Ctrl_Base_DepTag,
+                tc->setRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
                                       tidTCStatus, tid);
 
                 // Mark As Successful Fork
@@ -161,9 +163,10 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
     }
 
     if (success == 0) {
-        VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl);
+        VPEControlReg vpeControl =
+            tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
         vpeControl.excpt = 1;
-        tc->setMiscReg(VPEControl, vpeControl);
+        tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
         fault = new ThreadFault();
     }
 }
@@ -174,21 +177,24 @@ int
 yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
 {
     if (src_reg == 0) {
-        MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MVPConf0);
+        MVPConf0Reg mvpConf0 = tc->readMiscRegNoEffect(MISCREG_MVP_CONF0);
         ThreadID num_threads = mvpConf0.ptc + 1;
 
         int ok = 0;
 
         // Get Current VPE & TC numbers from calling thread
-        TCBindReg tcBind = tc->readMiscRegNoEffect(TCBind);
+        TCBindReg tcBind = tc->readMiscRegNoEffect(MISCREG_TC_BIND);
 
         for (ThreadID tid = 0; tid < num_threads; tid++) {
             TCStatusReg tidTCStatus =
-                tc->readRegOtherThread(TCStatus + Ctrl_Base_DepTag, tid);
+                tc->readRegOtherThread(MISCREG_TC_STATUS + Ctrl_Base_DepTag,
+                                       tid);
             TCHaltReg tidTCHalt =
-                tc->readRegOtherThread(TCHalt + Ctrl_Base_DepTag, tid);
+                tc->readRegOtherThread(MISCREG_TC_HALT + Ctrl_Base_DepTag,
+                                       tid);
             TCBindReg tidTCBind =
-                tc->readRegOtherThread(TCBind + Ctrl_Base_DepTag, tid);
+                tc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag,
+                                       tid);
 
             if (tidTCBind.curVPE == tcBind.curVPE &&
                 tidTCBind.curTC == tcBind.curTC &&
@@ -200,23 +206,24 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
         }
 
         if (ok == 1) {
-            TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
+            TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
             tcStatus.a = 0;
-            tc->setMiscReg(TCStatus, tcStatus);
+            tc->setMiscReg(MISCREG_TC_STATUS, tcStatus);
             warn("%i: Deactivating Hardware Thread Context #%i",
                     curTick, tc->threadId());
         }
     } else if (src_reg > 0) {
         if (src_reg && !yield_mask != 0) {
-            VPEControlReg vpeControl = tc->readMiscReg(VPEControl);
+            VPEControlReg vpeControl = tc->readMiscReg(MISCREG_VPE_CONTROL);
             vpeControl.excpt = 2;
-            tc->setMiscReg(VPEControl, vpeControl);
+            tc->setMiscReg(MISCREG_VPE_CONTROL, vpeControl);
             fault = new ThreadFault();
         } else {
         }
     } else if (src_reg != -2) {
-        TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
-        VPEControlReg vpeControl = tc->readMiscRegNoEffect(VPEControl);
+        TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
+        VPEControlReg vpeControl =
+            tc->readMiscRegNoEffect(MISCREG_VPE_CONTROL);
 
         if (vpeControl.ysi == 1 && tcStatus.dt == 1 ) {
             vpeControl.excpt = 4;
@@ -237,14 +244,14 @@ updateStatusView(TC *tc)
 {
     // TCStatus' register view must be the same as
     // Status register view for CU, MX, KSU bits
-    TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
-    StatusReg status = tc->readMiscRegNoEffect(Status);
+    TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
+    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
 
     status.cu = tcStatus.tcu;
     status.mx = tcStatus.tmx;
     status.ksu = tcStatus.tksu;
 
-    tc->setMiscRegNoEffect(Status, status);
+    tc->setMiscRegNoEffect(MISCREG_STATUS, status);
 }
 
 // TC will usually be a object derived from ThreadContext
@@ -255,14 +262,14 @@ updateTCStatusView(TC *tc)
 {
     // TCStatus' register view must be the same as
     // Status register view for CU, MX, KSU bits
-    TCStatusReg tcStatus = tc->readMiscRegNoEffect(TCStatus);
-    StatusReg status = tc->readMiscRegNoEffect(Status);
+    TCStatusReg tcStatus = tc->readMiscRegNoEffect(MISCREG_TC_STATUS);
+    StatusReg status = tc->readMiscRegNoEffect(MISCREG_STATUS);
 
     tcStatus.tcu = status.cu;
     tcStatus.tmx = status.mx;
     tcStatus.tksu = status.ksu;
 
-    tc->setMiscRegNoEffect(TCStatus, tcStatus);
+    tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
 }
 
 } // namespace MipsISA
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index b996b4717..fdb04b131 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -58,11 +58,11 @@ const uint32_t MIPS32_QNAN = 0x7fbfffff;
 const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
 
 enum FPControlRegNums {
-   FIR = NumFloatArchRegs,
-   FCCR,
-   FEXR,
-   FENR,
-   FCSR
+   FLOATREG_FIR = NumFloatArchRegs,
+   FLOATREG_FCCR,
+   FLOATREG_FEXR,
+   FLOATREG_FENR,
+   FLOATREG_FCSR
 };
 
 enum FCSRBits {
@@ -81,21 +81,21 @@ enum FCSRFields {
 };
 
 enum MiscIntRegNums {
-   LO = NumIntArchRegs,
-   HI,
-   DSPACX0,
-   DSPLo1,
-   DSPHi1,
-   DSPACX1,
-   DSPLo2,
-   DSPHi2,
-   DSPACX2,
-   DSPLo3,
-   DSPHi3,
-   DSPACX3,
-   DSPControl,
-   DSPLo0 = LO,
-   DSPHi0 = HI
+   INTREG_LO = NumIntArchRegs,
+   INTREG_DSP_LO0 = INTREG_LO,
+   INTREG_HI,
+   INTREG_DSP_HI0 = INTREG_HI,
+   INTREG_DSP_ACX0,
+   INTREG_DSP_LO1,
+   INTREG_DSP_HI1,
+   INTREG_DSP_ACX1,
+   INTREG_DSP_LO2,
+   INTREG_DSP_HI2,
+   INTREG_DSP_ACX2,
+   INTREG_DSP_LO3,
+   INTREG_DSP_HI3,
+   INTREG_DSP_ACX3,
+   INTREG_DSP_CONTROL
 };
 
 // semantically meaningful register indices
@@ -130,158 +130,158 @@ const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 // The first set of names classify the CP0 names as Register Banks
 // for easy indexing when using the 'RD + SEL' index combination
 // in CP0 instructions.
-enum MiscRegTags {
-    Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
-    MVPControl,
-    MVPConf0,
-    MVPConf1,
-
-    CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
-    VPEControl,
-    VPEConf0,
-    VPEConf1,
-    YQMask,
-    VPESchedule,
-    VPEScheFBack,
-    VPEOpt,
-
-    EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
-    TCStatus,
-    TCBind,
-    TCRestart,
-    TCHalt,
-    TCContext,
-    TCSchedule,
-    TCScheFBack,
-
-    EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
-
-    Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
-    ContextConfig,
-
-    PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
-    PageGrain = Ctrl_Base_DepTag + 41,
-
-    Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
-    SRSConf0,
-    SRSConf1,
-    SRSConf2,
-    SRSConf3,
-    SRSConf4,
-
-    HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
-
-    BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
-
-    Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
-
-    EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
-
-    Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
-
-    Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
-    IntCtl,
-    SRSCtl,
-    SRSMap,
-
-    Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
-
-    EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
-
-    PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
-    EBase,
-
-    Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
-    Config1,
-    Config2,
-    Config3,
-    Config4,
-    Config5,
-    Config6,
-    Config7,
-
-
-    LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
-
-    WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
-    WatchLo1,
-    WatchLo2,
-    WatchLo3,
-    WatchLo4,
-    WatchLo5,
-    WatchLo6,
-    WatchLo7,
-
-    WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
-    WatchHi1,
-    WatchHi2,
-    WatchHi3,
-    WatchHi4,
-    WatchHi5,
-    WatchHi6,
-    WatchHi7,
-
-    XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
+enum MiscRegIndex{
+    MISCREG_INDEX = 0,       //Bank 0: 0 - 3
+    MISCREG_MVP_CONTROL,
+    MISCREG_MVP_CONF0,
+    MISCREG_MVP_CONF1,
+
+    MISCREG_CP0_RANDOM = 8,      //Bank 1: 8 - 15
+    MISCREG_VPE_CONTROL,
+    MISCREG_VPE_CONF0,
+    MISCREG_VPE_CONF1,
+    MISCREG_YQMASK,
+    MISCREG_VPE_SCHEDULE,
+    MISCREG_VPE_SCHEFBACK,
+    MISCREG_VPE_OPT,
+
+    MISCREG_ENTRYLO0 = 16,   //Bank 2: 16 - 23
+    MISCREG_TC_STATUS,
+    MISCREG_TC_BIND,
+    MISCREG_TC_RESTART,
+    MISCREG_TC_HALT,
+    MISCREG_TC_CONTEXT,
+    MISCREG_TC_SCHEDULE,
+    MISCREG_TC_SCHEFBACK,
+
+    MISCREG_ENTRYLO1 = 24,   // Bank 3: 24
+
+    MISCREG_CONTEXT = 32,    // Bank 4: 32 - 33
+    MISCREG_CONTEXT_CONFIG,
+
+    MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41
+    MISCREG_PAGEGRAIN = 41,
+
+    MISCREG_WIRED = 48,          //Bank 6:48-55
+    MISCREG_SRS_CONF0,
+    MISCREG_SRS_CONF1,
+    MISCREG_SRS_CONF2,
+    MISCREG_SRS_CONF3,
+    MISCREG_SRS_CONF4,
+
+    MISCREG_HWRENA = 56,         //Bank 7: 56-63
+
+    MISCREG_BADVADDR = 64,       //Bank 8: 64-71
+
+    MISCREG_COUNT = 72,          //Bank 9: 72-79
+
+    MISCREG_ENTRYHI = 80,        //Bank 10: 80-87
+
+    MISCREG_COMPARE = 88,        //Bank 11: 88-95
+
+    MISCREG_STATUS = 96,         //Bank 12: 96-103
+    MISCREG_INTCTL,
+    MISCREG_SRSCTL,
+    MISCREG_SRSMAP,
+
+    MISCREG_CAUSE = 104,         //Bank 13: 104-111
+
+    MISCREG_EPC = 112,           //Bank 14: 112-119
+
+    MISCREG_PRID = 120,          //Bank 15: 120-127,
+    MISCREG_EBASE,
+
+    MISCREG_CONFIG = 128,        //Bank 16: 128-135
+    MISCREG_CONFIG1,
+    MISCREG_CONFIG2,
+    MISCREG_CONFIG3,
+    MISCREG_CONFIG4,
+    MISCREG_CONFIG5,
+    MISCREG_CONFIG6,
+    MISCREG_CONFIG7,
+
+
+    MISCREG_LLADDR = 136,        //Bank 17: 136-143
+
+    MISCREG_WATCHLO0 = 144,      //Bank 18: 144-151
+    MISCREG_WATCHLO1,
+    MISCREG_WATCHLO2,
+    MISCREG_WATCHLO3,
+    MISCREG_WATCHLO4,
+    MISCREG_WATCHLO5,
+    MISCREG_WATCHLO6,
+    MISCREG_WATCHLO7,
+
+    MISCREG_WATCHHI0 = 152,     //Bank 19: 152-159
+    MISCREG_WATCHHI1,
+    MISCREG_WATCHHI2,
+    MISCREG_WATCHHI3,
+    MISCREG_WATCHHI4,
+    MISCREG_WATCHHI5,
+    MISCREG_WATCHHI6,
+    MISCREG_WATCHHI7,
+
+    MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167
 
                        //Bank 21: 168-175
 
                        //Bank 22: 176-183
 
-    Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
-    TraceControl1,
-    TraceControl2,
-    UserTraceData,
-    TraceBPC,
+    MISCREG_DEBUG = 184,       //Bank 23: 184-191
+    MISCREG_TRACE_CONTROL1,
+    MISCREG_TRACE_CONTROL2,
+    MISCREG_USER_TRACE_DATA,
+    MISCREG_TRACE_BPC,
 
-    DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
+    MISCREG_DEPC = 192,        //Bank 24: 192-199
 
-    PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
-    PerfCnt1,
-    PerfCnt2,
-    PerfCnt3,
-    PerfCnt4,
-    PerfCnt5,
-    PerfCnt6,
-    PerfCnt7,
+    MISCREG_PERFCNT0 = 200,    //Bank 25: 200-207
+    MISCREG_PERFCNT1,
+    MISCREG_PERFCNT2,
+    MISCREG_PERFCNT3,
+    MISCREG_PERFCNT4,
+    MISCREG_PERFCNT5,
+    MISCREG_PERFCNT6,
+    MISCREG_PERFCNT7,
 
-    ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
+    MISCREG_ERRCTL = 208,      //Bank 26: 208-215
 
-    CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
-    CacheErr1,
-    CacheErr2,
-    CacheErr3,
+    MISCREG_CACHEERR0 = 216,   //Bank 27: 216-223
+    MISCREG_CACHEERR1,
+    MISCREG_CACHEERR2,
+    MISCREG_CACHEERR3,
 
-    TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
-    DataLo1,
-    TagLo2,
-    DataLo3,
-    TagLo4,
-    DataLo5,
-    TagLo6,
-    DataLo7,
+    MISCREG_TAGLO0 = 224,      //Bank 28: 224-231
+    MISCREG_DATALO1,
+    MISCREG_TAGLO2,
+    MISCREG_DATALO3,
+    MISCREG_TAGLO4,
+    MISCREG_DATALO5,
+    MISCREG_TAGLO6,
+    MISCREG_DATALO7,
 
-    TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
-    DataHi1,
-    TagHi2,
-    DataHi3,
-    TagHi4,
-    DataHi5,
-    TagHi6,
-    DataHi7,
+    MISCREG_TAGHI0 = 232,      //Bank 29: 232-239
+    MISCREG_DATAHI1,
+    MISCREG_TAGHI2,
+    MISCREG_DATAHI3,
+    MISCREG_TAGHI4,
+    MISCREG_DATAHI5,
+    MISCREG_TAGHI6,
+    MISCREG_DATAHI7,
 
 
-    ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
+    MISCREG_ERROR_EPC = 240,    //Bank 30: 240-247
 
-    DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
+    MISCREG_DESAVE = 248,       //Bank 31: 248-256
 
-    LLFlag = Ctrl_Base_DepTag + 257,
+    MISCREG_LLFLAG = 257,
 
-    NumControlRegs
+    MISCREG_NUMREGS
 };
 
 const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 
-const int NumMiscRegs = NumControlRegs;
+const int NumMiscRegs = MISCREG_NUMREGS;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 37c1ecee3..e01c06ae5 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -311,7 +311,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
     if (IsKSeg0(req->getVaddr())) {
         // Address will not be translated through TLB, set response, and go!
         req->setPaddr(KSeg02Phys(req->getVaddr()));
-        if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel ||
+        if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
                 req->isMisaligned()) {
             AddressErrorFault *Flt = new AddressErrorFault();
             /* BadVAddr must be set */
@@ -386,7 +386,7 @@ TLB::translateInst(RequestPtr req, ThreadContext *tc)
             }
         } else {
             // Didn't find any match, return a TLB Refill Exception
-            ItbRefillFault *Flt=new ItbRefillFault();
+            ItbRefillFault *Flt = new ItbRefillFault();
             /* EntryHi VPN, ASID fields must be set */
             Flt->entryHiAsid = Asid;
             Flt->entryHiVPN2 = (VPN >> 2);
@@ -431,7 +431,7 @@ TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
     if (IsKSeg0(req->getVaddr())) {
         // Address will not be translated through TLB, set response, and go!
         req->setPaddr(KSeg02Phys(req->getVaddr()));
-        if (getOperatingMode(tc->readMiscReg(Status)) != mode_kernel ||
+        if (getOperatingMode(tc->readMiscReg(MISCREG_STATUS)) != mode_kernel ||
                 req->isMisaligned()) {
             StoreAddressErrorFault *Flt = new StoreAddressErrorFault();
             /* BadVAddr must be set */
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 37cd838e5..1e58238e9 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -66,8 +66,8 @@ bool isSnan(void *val_ptr, int size);
 static inline bool
 inUserMode(ThreadContext *tc)
 {
-    MiscReg Stat = tc->readMiscReg(MipsISA::Status);
-    MiscReg Dbg = tc->readMiscReg(MipsISA::Debug);
+    MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
+    MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
 
     if ((Stat & 0x10000006) == 0 &&  // EXL, ERL or CU0 set, CP0 accessible
         (Dbg & 0x40000000) == 0 &&   // DM bit set, CP0 accessible