diff options
author | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-02-12 19:53:19 +0000 |
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committer | Timothy M. Jones <tjones1@inf.ed.ac.uk> | 2010-02-12 19:53:19 +0000 |
commit | dd60902152321a698682e4f53e29e4043ff321e5 (patch) | |
tree | 1a3944f6979e79f19de3aedcea36c2817ae507e8 /src | |
parent | 64999b43435cfee76823e36c23017efc5584b986 (diff) | |
download | gem5-dd60902152321a698682e4f53e29e4043ff321e5.tar.xz |
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/power/faults.hh | 16 | ||||
-rw-r--r-- | src/arch/power/tlb.cc | 32 | ||||
-rw-r--r-- | src/arch/power/tlb.hh | 2 |
3 files changed, 48 insertions, 2 deletions
diff --git a/src/arch/power/faults.hh b/src/arch/power/faults.hh index eadcb7900..0f49cc85d 100644 --- a/src/arch/power/faults.hh +++ b/src/arch/power/faults.hh @@ -76,6 +76,22 @@ class MachineCheckFault : public PowerFault }; +class AlignmentFault : public PowerFault +{ + public: + AlignmentFault() + : PowerFault("Alignment") + { + } + + bool + isAlignmentFault() const + { + return true; + } +}; + + static inline Fault genMachineCheckFault() { diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc index 125c92a1a..292f13078 100644 --- a/src/arch/power/tlb.cc +++ b/src/arch/power/tlb.cc @@ -281,9 +281,27 @@ TLB::regStats() } Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +TLB::translateInst(RequestPtr req, ThreadContext *tc) +{ + // Instruction accesses must be word-aligned + if (req->getVaddr() & 0x3) { + DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), + req->getSize()); + return new AlignmentFault(); + } + + Process * p = tc->getProcessPtr(); + + Fault fault = p->pTable->translate(req); + if (fault != NoFault) + return fault; + + return NoFault; +} + +Fault +TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) { -#if !FULL_SYSTEM Process * p = tc->getProcessPtr(); Fault fault = p->pTable->translate(req); @@ -291,6 +309,16 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) return fault; return NoFault; +} + +Fault +TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) +{ +#if !FULL_SYSTEM + if (mode == Execute) + return translateInst(req, tc); + else + return translateData(req, tc, mode == Write); #else fatal("translate atomic not yet implemented\n"); #endif diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index 8b6c7233d..1794de626 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -156,6 +156,8 @@ class TLB : public BaseTLB // static helper functions... really static bool validVirtualAddress(Addr vaddr); static Fault checkCacheability(RequestPtr &req); + Fault translateInst(RequestPtr req, ThreadContext *tc); + Fault translateData(RequestPtr req, ThreadContext *tc, bool write); Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); void translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode); |